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Deriving approximation tolerance constraints from verification runs [article]

Tobias Isenberg, Marie-Christine Jakobs, Felix Pauck, Heike Wehrheim
2016 arXiv   pre-print
On the practical side, we furthermore (1) show how to extract tolerance constraints from verification runs employing predicate abstraction as an instance of abstract interpretation, and (2) show how to  ...  In contrast to all existing approaches, we start with a standard program verification and compute the allowed tolerances for AC hardware from that verification run.  ...  Its basic principle is the derivation of constraints on AC hardware from verification runs.  ... 
arXiv:1604.08784v2 fatcat:4fzsxhxv4fhq7dsffljaluqow4

Online Verification of Deep Neural Networks under Domain or Weight Shift [article]

Tianhao Wei, Changliu Liu
2021 arXiv   pre-print
However, it is still challenging to run existing verification algorithms online.  ...  We propose three types of techniques (branch management, perturbation tolerance analysis, and incremental computation) to accelerate the online verification of deep neural networks.  ...  Temporal dependencies To run online verification of (1) efficiently, we need to leverage temporal dependencies of the online problems.  ... 
arXiv:2106.12732v1 fatcat:o7c7asb42rgt5h46huhuhiuuxm

Power grid verification using node and branch dominance

Nahi Abdul Ghani, Farid N. Najm
2011 Proceedings of the 48th Design Automation Conference on - DAC '11  
This work describes a vectorless verification technique that deals with circuit uncertainty in the framework of current constraints.  ...  Results show a dramatic reduction in the number of LPs thus making vectorless grid verification in the framework of current constraints practical and scalable.  ...  and k > 0 is an internal error tolerance that is derived from another user-specified error-tolerance, δ, on voltages, based on: k = δ u T k i L + u T i L , ∀k = 1, . . . , n (18) where u is an n × 1 vector  ... 
doi:10.1145/2024724.2024879 dblp:conf/dac/GhaniN11 fatcat:moqpzlagnvenveaxdw4xarrfty

Formal verification of algorithms for critical systems

J.M. Rushby, F. von Henke
1993 IEEE Transactions on Software Engineering  
We indicate the errors we found in the published analysis of the algorithm, and other benefits that we derived from the verification.  ...  Based on our experience, we derive some key requirements for a formal specification and verification system adequate to the task of verifying algorithms of the type considered.  ...  Ricky Butler of NASA Langley Research Center provided valuable encouragement and guidance in our study of fault-tolerant algorithms.  ... 
doi:10.1109/32.210304 fatcat:6rj6472x6vcwbgxm2forlk542y

Formal verification of algorithms for critical systems

John Rushby, Friedrich von Henke
1991 Proceedings of the conference on Software for citical systems - SIGSOFT '91  
We indicate the errors we found in the published analysis of the algorithm, and other benefits that we derived from the verification.  ...  Based on our experience, we derive some key requirements for a formal specification and verification system adequate to the task of verifying algorithms of the type considered.  ...  Ricky Butler of NASA Langley Research Center provided valuable encouragement and guidance in our study of fault-tolerant algorithms.  ... 
doi:10.1145/125083.123044 fatcat:7mjftfwqdjbypn6kw7xzjli34m

Formal verification of algorithms for critical systems

John Rushby, Friedrich von Henke
1991 Software engineering notes  
We indicate the errors we found in the published analysis of the algorithm, and other benefits that we derived from the verification.  ...  Based on our experience, we derive some key requirements for a formal specification and verification system adequate to the task of verifying algorithms of the type considered.  ...  Ricky Butler of NASA Langley Research Center provided valuable encouragement and guidance in our study of fault-tolerant algorithms.  ... 
doi:10.1145/123041.123044 fatcat:umkxh5xpdfawrbepekjkmwnde4

Formal modeling of BPEL workflows including fault and compensation handling

Máté Kovács, Dániel Varró, László Gönczy
2007 Proceedings of the 2007 workshop on Engineering fault tolerant systems - EFTS '07  
BPEL) Widespread tool support Verification techniques still need improvement Design errors of orchestration Our aim: Check requirements on workflows formally Derive formal models by model transformations  ...  Ready Activated Running Faulthandling Compensating Finished Completed with fault Compensated Constraints of Activity Triggering … AND scope_1=faulthandling AND scope_2=compensating AND  ... 
doi:10.1145/1316550.1316551 dblp:conf/sigsoft/KovacsVG07 fatcat:o2lmxsldnjdhvml2ewfzvs3hpe

Faster projection based methods for circuit level verification

Chao Yan, Mark Greenstreet
2008 2008 Asia and South Pacific Design Automation Conference  
This motivates the verification of digital circuits using continuous models.  ...  Recently, we showed how such verification can be performed using projection based methods.However, the verification was slow, requiring nearly four CPU days to verify a nine-transistor toggle flip-flop  ...  First, we would like to compare our verification result and run-time with those from other verification tools.  ... 
doi:10.1109/aspdac.2008.4483985 dblp:conf/aspdac/YanG08a fatcat:g7vzs76fnrcgnnmaangcyr36da

A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification

Wei Zhao, Yici Cai, Jianlei Yang
2013 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)  
In this paper, we propose a new algorithm that combines the matrix-based technique and the multilevel method to construct a data-sparse approximate inverse of the power grid matrix.  ...  Vectorless power grid verification technique makes it possible to estimate the worst-case voltage fluctuations of the on-chip power delivery network at the early design stage.  ...  And the current constraints have also been extended from DC constraints to transient constraints [8] .  ... 
doi:10.1109/aspdac.2013.6509590 dblp:conf/aspdac/ZhaoCY13 fatcat:bb3vhyqmjzg4ticch2nnawtef4

Certifying Solutions for Numerical Constraints [chapter]

Eva Darulova, Viktor Kuncak
2013 Lecture Notes in Computer Science  
Among the aspects that make verification in this domain difficult is the need to quantify numerical errors, such as roundoff errors and errors due to the use of approximate numerical methods.  ...  Our technique combines runtime verification approaches with information about the analytical equation being solved.  ...  In contrast, we use the theorems from Section 3 as a verification method that accepts solutions computed by an arbitrary method.  ... 
doi:10.1007/978-3-642-35632-2_27 fatcat:4tfavvvy25bv7kgr3jeekbk57q

Exploiting bounds optimization for the semi-formal verification of analog circuits

Ons Lahiouel, Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar
2017 Integration  
Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time.  ...  This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques.  ...  500 LHS runs Upper bound from 500 LHS runs Lower bound from WCA Upper bound from WCA Lower bound from 500 QMC runs Upper bound from 500 QMC runs Upper bound from CA Lower bound from CA Fig. 17: Lower  ... 
doi:10.1016/j.vlsi.2017.06.008 fatcat:4yyetoiohnc55dsnhprz6zmewm

Test Results for an Interval Branch and Bound Algorithm for Equality-Constrained Optimization [chapter]

R. Baker Kearfott
1996 Nonconvex Optimization and Its Applications  
The underlying implementation includes use of an approximate optimizer combined with a careful tesselation process and rigorous verification of feasibility.  ...  Also in [20] , it was observed that, typically, the number of coordinates not corresponding to active bound constraints was less than the number of equality constraints; since verification that a point  ...  We believe this to be due to our use of an approximate optimizer, combined with Algorithm 2 and our choice of tolerances.  ... 
doi:10.1007/978-1-4613-3437-8_12 fatcat:q5o4kq6u4bejrj5purenlcnp3e

Balancing Scalability and Uniformity in SAT Witness Generator

Supratik Chakraborty, Kuldeep S. Meel, Moshe Y. Vardi
2014 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14  
The effectiveness of this approach depends on two key factors: the quality of constraints used to generate test vectors, and the randomness of solutions generated from a given set of constraints.  ...  Constrained-random simulation is the predominant approach used in the industry for functional verification of complex digital designs.  ...  the source domain from which the CNF formula F is derived.  ... 
doi:10.1145/2593069.2593097 dblp:conf/dac/ChakrabortyMV14 fatcat:a2cizjkjk5aqforekz4bja6krm

Exploiting Execution Dynamics in Timing Analysis Using Job Sequences

Leonie Ahrendts, Rolf Ernst, Sophie Quinton
2018 IEEE design & test  
This paper outlines existing modeling and analysis techniques which are based on job sequences and refers to several examples from automotive design where great benefits were demonstrated.  ...  ACKNOWLEDGMENTS This work has received funding from the German Research Foundation (DFG) under the contract number TWCA ER168/30-1.  ...  First, event arrival curves and workload curves for each task are derived, which are true upper bounds for most of the run time.  ... 
doi:10.1109/mdat.2017.2746638 fatcat:mnxr5i2oxrcghndbkkw4jgfwa4

Experiences from Large-Scale Model Checking: Verification of a Vehicle Control System [article]

Jonas Fritzsch, Tobias Schmid, Stefan Wagner
2020 arXiv   pre-print
Here, formal verification as a long established technique can be an appropriate complement.  ...  Safety aspects become more important and require such systems to operate with the highest possible level of fault tolerance.  ...  They formulate specifications in Linear Temporal Logic (LTL) that are derived from a STPA safety analysis.  ... 
arXiv:2011.10351v1 fatcat:lpg2fq5mofgc7puvrgqwsuiig4
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