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Energy-efficient computing with heterogeneous multi-cores
2014
2014 International Symposium on Integrated Circuits (ISIC)
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Homogeneous multi-cores, while ubiquitous today, cannot provide the desired performance and energyefficiency for various application domains. ...
This paper describes heterogeneous multi-core architectures and the runtime management strategies to leverage the potential of such architectures for improved energy-efficiency. ...
on the appropriate cores for better energy efficiency. ...
doi:10.1109/isicir.2014.7029584
dblp:conf/isicir/Mitra14
fatcat:oqcovqjrdfbd5jo6pdqm3h2y5u
Load balancing strategy for multicore systems
2015
2015 13th International Conference on Emerging eLearning Technologies and Applications (ICETA)
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Soft-wares are written for multicore platform that distribute the workload amongst multiple identical or different cores. This functionality is called thread-level parallelism. ...
This is not only to the rising energy cost but these systems are playing a major role in global warming and greenhouse gas emissions. ...
Rishma Sadaf for her review and valuable comments. ...
doi:10.1109/iceta.2015.7558473
fatcat:ffoxzd7j6jc4loehhunoppfhwe
A Task-level Pipelined Many-SIMD Augmented Reality Processor with Congestion-aware Network-on-Chip Scheduler
2015
IEEE Micro
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As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state-of-the-art augmented reality processor, for 30fps 720p test input video ...
In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task-level pipeline. ...
Conclusion For the first time, a recognition-based markerless AR processor is proposed with congestion-aware scheduler for 2D-mesh NoC architecture. ...
doi:10.1109/mm.2015.2
fatcat:kd5kg5ndxne3hksvlxzkrq2nne
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler
2014
2014 IEEE COOL Chips XVII
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As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state-of-the-art augmented reality processor, for 30fps 720p test input video ...
In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task-level pipeline. ...
Conclusion For the first time, a recognition-based markerless AR processor is proposed with congestion-aware scheduler for 2D-mesh NoC architecture. ...
doi:10.1109/coolchips.2014.6842959
dblp:conf/coolchips/KimPLKHBSCPY14
fatcat:e3ms3usrrfabdjo77lssrttaxy
Author index
2006
2006 IEEE International Conference on Cluster Computing
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Hotta, Yoshihiko
Empirical Study on Reducing Energy of Parallel Programs using
Slack Reclamation by DVFS in a Power-scalable High Performance
Cluster
Huard, Guillaume
I/O Scheduling Service for Multi-Application ...
Using Simulation, Historical and Hybrid Estimation Systems for
Enhacing Job Scheduling on NOWs
Sowa, Przemyslaw
I/O Scheduling Service for Multi-Application Clusters
Spooner, Daniel P. ...
doi:10.1109/clustr.2006.311921
fatcat:vmbbimypuze7ncjqfonu4po5l4
Architecture-aware configuration and scheduling of matrix multiplication on asymmetric multicore processors
2016
Cluster Computing
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Quintana-Ortí) gains in performance with respect to its architecture-oblivious counterparts while exploiting all the resources of the AMP to deliver considerable energy efficiency. ...
Our solution is based on the reference implementation of gemm in the BLIS library, and integrates a cache-aware configuration as well as asymmetric-static and dynamic scheduling strategies that carefully ...
We note that, when calculating the energy efficiency of one type of cluster, the energy consumed by the complementary (idle) cluster is also accounted for, so that we are reporting the energy efficiency ...
doi:10.1007/s10586-016-0611-8
fatcat:vvazo73u4rfttmqbrt34mdwvie
Architecture-Aware Configuration and Scheduling of Matrix Multiplication on Asymmetric Multicore Processors
[article]
2015
arXiv
pre-print
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scheduling attain important gains in performance with respect to its architecture-oblivious counterparts while exploiting all the resources of the AMP to deliver considerable energy efficiency. ...
Our solution is based on the reference implementation of gemm in the BLIS library, and integrates a cache-aware configuration as well as asymmetric--static and dynamic scheduling strategies that carefully ...
We note that, when calculating the energy efficiency of one type of cluster, the energy consumed by the complementary (idle) cluster is also accounted for, so that we are reporting the energy efficiency ...
arXiv:1506.08988v1
fatcat:z3t6tw6w4reo3jjfsseyqssjgi
Dynamic Task Scheduling Methods in Heterogeneous Systems: A Survey
2015
International Journal of Computer Applications
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A Parallel application can be represented by a Directed Acyclic Graph (DAG), which represents the dependency among tasks, based on their execution time and communication time. ...
Previous studies reveal that many researchers have designed efficient scheduling algorithms with different parameters on multiprocessor systems. ...
CBHD Algorithm Abdelkader and Omara proposed Clustering based HEFT with Duplication, used for efficient scheduling and mapping for tasks on heterogeneous systems, to break the program into subtasks and ...
doi:10.5120/19318-0859
fatcat:qxnjvseeajcyfiyzdq4xxtonw4
Heterogeneous Multi-core Architectures
2015
IPSJ Transactions on System LSI Design Methodology
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Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on. ...
This article presents an overview of the state-of-the-art in heterogeneous multi-core landscape. ...
on the appropriate cores for better energy efficiency. ...
doi:10.2197/ipsjtsldm.8.51
fatcat:wgiuptlmvvgnhdt2bjrcio6oqi
Energy Saving Approaches for Scheduling on Parallel Systems: A Review
2016
International Journal of Computer Applications
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One of them is scheduling. Scheduling is frequently required in parallel systems (Distributed System, Embedded System and Multi -core System). ...
Scheduling is a method by which task accesses the resources of the parallel system. It is efficient to choose such a method by which one can get optimum schedule length with less energy consumption. ...
Bautista et al presented a novel power-aware scheduling algorithm for multi-core processor addressing soft real-time applications. ...
doi:10.5120/ijca2016911798
fatcat:qwvt2inypnh6nbvf7rshf5sa3y
Understanding the Impact of vCPU Scheduling on DVFS-Based Power Management in Virtualized Cloud Environment
2014
2014 IEEE 22nd International Symposium on Modelling, Analysis & Simulation of Computer and Telecommunication Systems
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In addition, newly created vCPUs, if scheduled solely based on fairness, can cause inefficient frequency rise and drop on an unmatched physical core, which we refer to as utilization mismatch problem. ...
We also show that dirty page rate, virtual block device processing rate, virtual network packets arrival rate, and network I/O buffer availability are important efficiency indicators for energy-efficient ...
This work is supported in part by NSF grants 1320100, 1117261, 0845721(CAREER), and by Microsoft Research Safe and Scalable Multi-core Computing Awards. ...
doi:10.1109/mascots.2014.44
dblp:conf/mascots/LiuLL14
fatcat:uv6zrixirjgkzbfbluzw7wlona
Exploring parallelization for medium access schemes on many-core software defined radio architecture
2013
Proceedings of the second workshop on Software radio implementation forum - SRIF '13
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Therefore, in this paper, we explore how a homogeneous SDR architecture is used for efficient realization and execution of Medium Access Control (MAC) protocols. ...
We provide a toolchain which utilizes the characteristics of P2012 for MAC parallelization, runtime scheduling, and execution. ...
Heterogeneous multi-core architecture is popular for its power efficiency, high performance and low cost. ...
doi:10.1145/2491246.2491250
dblp:conf/sigcomm/ZhangAAM13
fatcat:dashdootlffg3pnekdpyygzl74
Energy efficient computing, clusters, grids and clouds: A taxonomy and survey
2017
Sustainable Computing: Informatics and Systems
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Key findings include: (i) in clusters and grids, use of system level efficiency techniques might increase their energy consumption; (ii) in (virtualized) clouds, efficient scheduling and resource allocation ...
can lead to substantially greater economies than consolidation through migration; and (iii) in clusters, switching off idle resources is more energy efficient, however in (production) clouds, performance ...
Joseph Chrol-Cannon and Santosh Tirunagari from Department of Computer Science, University of Surrey, UK for their review, valuable comments, and suggestions for technical improvement of this work in hand ...
doi:10.1016/j.suscom.2017.03.002
fatcat:fqkd6lmovjhabboo5f2mh5qsby
On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC
2016
2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)
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However, the ever greater demand for energy efficiency fosters energy budgeting in MP2SoC systems. ...
The originality of this approach is that it integrates the Energy-Aware Duplication (EAD) algorithm that strives to balance schedule lengths and energy savings by considering the most important sources ...
The central feature of the rapid prototyping method is the multi-core scheduler. ...
doi:10.1109/pdp.2016.110
dblp:conf/pdp/AmmarBPDA16
fatcat:2kjcsbunfnhsnjf3anke6pl7fm
AAP4All: An Adaptive Auto Parallelization of Serial Code for HPC Systems
2021
Intelligent Automation and Soft Computing
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However, the modern HPC systems are configured by adding the powerful and energy efficient multi-cores/many-cores parallel computing devices such as GPUs, MIC, and FPGA etc. ...
Due to increasing the complexity of one chip many-cores/multi-cores systems, only well-balanced and optimized parallel programming technique is the solution to provide substantial increase in performance ...
Acknowledgement: The authors, acknowledge with thanks DSR King Abdulaziz University, Jeddah, Saudi Arabia for technical and financial support. ...
doi:10.32604/iasc.2021.019044
fatcat:quu46dwokbf2fkq24jrtp7uo7i
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