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The Delay-Insensitivity, the Hazard-Freedom, the Semi-Modularity and the Technical Condition of Good Running of the Discrete Time Asynchronous Automata [article]

Serban E. Vlad
2001 arXiv   pre-print
The paper studies some important properties of the asynchronous (=timed) automata: the delay-insensitivity, the hazard-freedom, the semi-modularity and the technical condition of good running.  ...  Proposition If g is semi-modular in w , then it is also weakly semi-modular in w . Proof Let } ,..., 1 { ), ( n i w l ∈ ∈ L and 0 ≥ k .  ...  If one of 3.2 a) , b), c) is true, then g is delay-insensitive in w . We say that g transfers w in w in a delay-insensitive manner and that the transfer w w→ is delayinsensitive.  ... 
arXiv:cs/0110062v1 fatcat:x2qlwc2gtvfolppsnmm7ymohge

Semi-modular delay model revisited in context of relative timing

Hoon Park, Marly Roncken, Anping He, Xiaoyu Song
2015 Electronics Letters  
We present a new definition of semi-modularity to accommodate relative timing constraints in self-timed circuits.  ...  The old definition produces a false semi-modularity conflict that cannot exist due to the set of imposed constraints. The new definition correctly accepts the solution.  ...  Focus shifted to speed and energy efficiency, which were achieved by exchanging delay-insensitivity for extra delay assumptions formulated as relative timing constraints [5, 6, 7, 8, 9] .  ... 
doi:10.1049/el.2014.3666 fatcat:3nqzrv53wbfcthfvmd3dik6tbe

Delay-insensitivity and ternary simulation

J.A. Brzozowski
2000 Theoretical Computer Science  
If such a network exists, we say that it implements delay-insensitively.  ...  In this paper we survey the known results concerning delay-insensitivity, and outline one proof that a simple speciÿcation cannot be implemented. : S 0 3 0 4 -3 9 7 5 ( 9 9 ) 0 0 2 7 3 -X  ...  Acknowledgements The author wishes to thank David Dill, Jo Ebergen, Mark Josephs, Luciano Lavagno, Jan Tijmen Udding, Tom Verhoe , Hao Zhang, and an anonymous referee for their comments on this paper.  ... 
doi:10.1016/s0304-3975(99)00273-x fatcat:g3w4zawmo5c27ioaaher3kwz5a

Verifying and Testing Asynchronous Circuits Using Lotos [chapter]

Ji He, Kenneth J. Turner
2000 IFIP Advances in Information and Communication Technology  
The approach is illustrated with three case studies that explore speed independence, delay sensitivity and testing of sample asynchronous circuit designs.  ...  An algorithm is also presented for generating and applying implementation tests based on a specification. Tools have been developed for automated verification of conformance and generation of tests.  ...  Semi-modularity is commonly used as a correctness criterion for speed independence, since the violation of semi-modularity causes speed-dependent behaviour.  ... 
doi:10.1007/978-0-387-35533-7_17 fatcat:4jy7uxlrnngz3e2gk7ob6raw3q

Page 6326 of Mathematical Reviews Vol. , Issue 2002H [page]

2002 Mathematical Reviews  
Summary: “The paper defines and characterizes the delay- insensitivity, the hazard-freedom, the semi-modularity and the technical condition of good running of discrete time asyn- chronous automata.”  ...  The delay-insensitivity, the hazard-freedom, the semi-modularity and the technical condition of good running of the discrete time asynchronous automata. (English summary) An. Univ. Oradea Fasc.  ... 

Automata of asynchronous behaviors

J.A. Brzozowski, R. Negulescu
2000 Theoretical Computer Science  
The applications are: veriÿcation of concurrent processes, liveness properties, and delay insensitivity of asynchronous networks.  ...  For process veriÿcation, we describe a BDD-based tool that implements the respective automata and operations.  ...  A delay-dense network N is delay-insensitive i its network automaton N is semi-modular.  ... 
doi:10.1016/s0304-3975(99)00021-3 fatcat:jel3d5iaxfhz5awgqs447grlni

Basic gate implementation of speed-independent circuits

Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alex Yakovlev
1994 Proceedings of the 31st annual conference on Design automation conference - DAC '94  
Existing methods for synthesis of speedindependent circuits under unbounded delay model have difficulties in combining the generality of formal approach with the practicality of the implementation architectures  ...  presents a characteristic property of the state graph specification, called Monotonous Cover requirement, implying its hazard-free implementation within the standard structure of a two-level SOP logic and  ...  RS-and C-implementations are semi-modular.  ... 
doi:10.1145/196244.196275 dblp:conf/dac/KondratyevKLVY94 fatcat:t7cphzxmuvbkngcmnjji62eraa

Externally hazard-free implementations of asynchronous circuits

Milton Sawasaki, Chantal Ykman-Couvreur, Bill Lin
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
We formally prove that within this architecture a very wide class of semi-modular state graphs with input choices (either distributive or non-distributive) that satisfy the complete state coding property  ...  This represents a significant departure from most existing methods that require the combinational logic to be hazard-free and are mainly valid for distributive behaviors.  ...  (b) Non single traversal SG An SG is semi-modular with input choices if and only if (8t1 2 TO) and (8t2 2 T) and (8s 2 S), we have s[t1i and s[t2i ) 9 s 0 2 S : s t 1 t 2 ! s 0 and s t 2 t 1 !  ... 
doi:10.1145/217474.217617 dblp:conf/dac/SawasakiYL95 fatcat:zalk2cvyrbcnvg2ebni22bussq

Externally Hazard-Free Implementations of Asynchronous Circuits

Milton Sawasaki
1995 Proceedings - Design Automation Conference  
We formally prove that within this architecture a very wide class of semi-modular state graphs with input choices (either distributive or non-distributive) that satisfy the complete state coding property  ...  This represents a significant departure from most existing methods that require the combinational logic to be hazard-free and are mainly valid for distributive behaviors.  ...  (b) Non single traversal SG An SG is semi-modular with input choices if and only if (8t1 2 TO) and (8t2 2 T) and (8s 2 S), we have s[t1i and s[t2i ) 9 s 0 2 S : s t 1 t 2 ! s 0 and s t 2 t 1 !  ... 
doi:10.1109/dac.1995.250058 fatcat:ymtgzfipsfgpdkbmq2v6s52pya

The Future of Formal Methods and GALS Design

Kenneth S. Stevens, Daniel Gebhardt, Junbok You, Yang Xu, Vikas Vij, Shomit Das, Krishnaji Desai
2009 Electronical Notes in Theoretical Computer Science  
The System-on-Chip era has arrived, and it arrived quickly. Modular composition of components through a shared interconnect is now becoming the standard, rather than the exotic.  ...  , and the ever present tradeoff between greed and fear.  ...  Each component in this system uses semi-modular specifications [23, 14] , and are modeled in CCS process language which supports nondeterminism.  ... 
doi:10.1016/j.entcs.2009.07.032 fatcat:7ae2rt6twfei7iyxmknd7t7poi

Characterization of Asynchronous Templates for Integration into Clocked CAD Flows

Kenneth S. Stevens, Yang Xu, Vikas Vij
2009 2009 15th IEEE Symposium on Asynchronous Circuits and Systems  
Thus most commercial work relies on custom CAD or untimed delay-insensitive design methodologies.  ...  Asynchronous circuit design can result in substantial benefits of reduced power, improved performance, and high modularity.  ...  The semi-modular specification of a 2-input NAND gate. Inputs that would disable an output are not permitted. This creates semi-modular computation interference errors in the verification.  ... 
doi:10.1109/async.2009.26 dblp:conf/async/StevensXV09 fatcat:suslhojq5nd3xh3zjx3bq7krga

Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results [article]

P Balasubramanian, D L Maskell, N E Mastorakis
2019 arXiv   pre-print
Compared to the best of existing semi-custom asynchronous carry lookahead adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries  ...  achieves 13% reduction in forward latency and 14.8% reduction in cycle time compared to the best of the existing CLAs featuring redundant carries with no area or power penalty.  ...  Isochronic forks represent the weakest compromise to delay-insensitivity.  ... 
arXiv:1901.09315v1 fatcat:42zcveogdrdnhfhgz2fk7tkpha

Automated Verification of Asynchronous Circuits Using Circuit Petri Nets

Ivan Poliakov, Andrey Mokhov, Ashur Rafiev, Danil Sokolov, Alex Yakovlev
2008 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems  
The method has been automated and compared against previously existing circuit verification tools. 14th IEEE International Symposium on Asynchronous Circuits and Systems 1522-8681/08 $25.00  ...  Once the circuit Petri net is constructed and composed with the provided environment specification, the presence and reachability of troublesome states is verified by using methods based on finite prefixes  ...  The authors would like to thank Victor Khomenko for many fruitful discussions regarding Petri net unfoldings, and for his help with PUNF and MPSAT tools, Tomohiro Yoneda for the quick response and valuable  ... 
doi:10.1109/async.2008.18 dblp:conf/async/PoliakovMRSY08 fatcat:vnsafsj5argkpgof2nm34xunye

Modeling and design of asynchronous circuits

M.B. Josephs, S.M. Nowick, C.H. Van Berkel
1999 Proceedings of the IEEE  
operation that is free from glitches. 3) Various notations are available for specification of control circuitry and as a starting point for logic synthesis. 4) Bundled data and delay-insensitive coding  ...  This technology review explores the behavioral and structural design domains for asynchronous circuits and systems.  ...  The same problem arises, in different guises, in both burst-mode (function hazards) and SI methods (violation of semi-modular constraints).  ... 
doi:10.1109/5.740017 fatcat:ud3rqhiozja6rkf5prhsnvr35q

Symbolic verification of timed asynchronous hardware protocols

Krishnaji Desai, Kenneth S. Stevens, John O'Leary
2013 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)  
SAT based and BDD based methods are explored employing both interleaving and simultaneous compositions.  ...  A methodology and automated tool flow have been developed for verifying systems of timed asynchronous circuits through compositional model checking of formal models with symbolic methods.  ...  Failure Reachability We model timed protocols with semi-modular processes [10] .  ... 
doi:10.1109/isvlsi.2013.6654650 dblp:conf/isvlsi/DesaiSO13 fatcat:bd3xxuhzdreqxi4eahq53icctq
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