Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes.

The key to enabling the cost-effective use of m-of-n codes is to find a suitable mapping of the binary data to the code. ... m-of-n codes can be used for carrying data over selftimed on-chip interconnect links. Such codes can be chosen to have low redundancy, but the costs of encoding/decoding data is high. ... Typically a point-to-point interconnect as illustrated in figure 1 will be many bits wide, requiring multiple selftimed code-groups as illustrated in figure 2 to carry the data word to give DI operation ...

doi:10.1109/async.2003.1199173 dblp:conf/async/BainbridgeTEF03 fatcat:pkwrcj3n7vgp7a4bvge6vagnoe

In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. ... Our solution is based on the Berger coding scheme and allows to obtain a very low wire overhead. ... proposed an implementation of a delay-insensitive chip area interconnect using dual rail encoding. Bainbridge et al. proposed a m-of-n scheme for point-to-point on-chip links [14] . ...

doi:10.1109/date.2006.243842 dblp:conf/date/CampobelloCCM06 fatcat:zugwj77mnjc2vjahzdwlcw6nhy

With increasing clock frequencies, the signal delay on some interconnects in an SoC often exceeds the clock period which necessitates latency insensitive protocols (LIPs). ... We believe this is a useful framework in the hands of designers trying to create new LIPs or optimizing existing ones for design convergence. ... Depending on the delay of the interconnect, the events can be compared from the point they are placed on the signal to the point they leave the signal. 6. ...

doi:10.1109/tc.2006.188 fatcat:rhv2dqnf2ncfpn3o4zwj3ykx2a

Due to the spatial and temporal distribution of switching activities in delay-insensitive asynchronous circuits, the thermal density as well as the temperature is largely reduced. ... Results show that the sample delay-insensitive asynchronous circuit exhibits lower average temperature and more uniform thermal distribution compared to it's synchronous counterpart. ... In this paper the thermal distributions of synchronous and delay-insensitive asynchronous 32-bit floating-point coprocessors are investigated and compared. ...

doi:10.1109/3dic.2009.5306544 dblp:conf/3dic/HollosiZNXDS09 fatcat:oen6bnsk5fbkxm2fi4capgc2yq

This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep submicron point-to-point interconnects. ... Moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput. ... It is important to mention that the delay approximation for the driving point is fairly insensitive to the value of the driver resistance [5] . ...

doi:10.1145/1233501.1233565 dblp:conf/iccad/MurganMOG06 fatcat:oo53hkyogjandcte44vaunkjdu

This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep submicron point-to-point interconnects. ... Moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput. ... It is important to mention that the delay approximation for the driving point is fairly insensitive to the value of the driver resistance [5] . ...

doi:10.1109/iccad.2006.320053 fatcat:npb5kss55zcktmybkntpozgkti

In comparison to the most coding-efficient non-systematic DI code (i.e. m-of-n), the DI bus-invert code had similar coding efficiency and number of wire transitions per transaction, but with significantly ... A new class of delay-insensitive (DI) codes, called DI Bus-Invert, is introduced for timing-robust global asynchronous communication. ... The Berger Bus-Invert code uses a straightforward extension of the Stan/Burleson method to provide delay-insensitivity. ...

doi:10.1109/date.2011.5763221 dblp:conf/date/AgyekumN11 fatcat:fc4hccwh7bhhdgqfxbpkpu5w5e

The reason why one needs to implement LIPs on long interconnects stems from the fact that with increasing clock frequencies, the signal delay on some interconnects exceeds the clock period. ... Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. ... We start with a collection of synchronously communicating components. These components can be custom-made modules or IP cores. ...

doi:10.1016/j.entcs.2005.05.041 fatcat:dw33jovjivejllll7zjhy22rhm

Open Access

Since any physical variation in an electrical parameter may have its own negative effect on the timing behavior of the circuit, being able to design delay-insensitive circuits (i.e., correct operation ... The proposed 11 www.intechopen.com Cutting Edge Nanotechnology 226 asynchronous nano-architecture is based on delay-insensitive data encoding and self-timed logic referred to as the Null Convention Logic ... delay-insensitive combination logic circuit (Fig.13 ). ...

doi:10.5772/8857 fatcat:rfyqfdfoibegxkbjnfu5wimg7q

Gate and interconnect delays are a typical example. ... This article proposes an on-chip point-to-point interconnect scheme characterized by self-calibration that can operate dynamically to achieve the best energy/performance trade-off. ... Instead of more-classical delayinsensitive encodings, such as 1-of-N schemes, we use the simpler scheme shown in Figure 5 . ...

doi:10.1109/mdt.2004.96 fatcat:svq7jc7xxvf3fl7twgbndhsxsy

In such cases, point-to-point connections between routers must be latency insensitive to cope with excessive wire delays. 6 Recent research, inspired by the original idea of latency insensitivity, applies ... We calculate the system's throughput, evaluated as the average number of unstalled computations per clock cycle, as the worst ratio m/(m + n) of the netlist graph, where m is the number of blocks in a ...

doi:10.1109/mdt.2007.152 fatcat:b5cnx2552jaale6txnagytb7sy

We demonstrate it is possible to achieve a similar number of transitions per bit as existing delay insensitive codes, from a power consumption point of view, but achieving resilience to transient faults ... The link has been synthesized and validated using 0.12 µm technology and power, area and performance are given. ... Acknowledgements The authors would like to acknowledge the Engineering and Physical Sciences Research Council (EPSRC) for funding under grant no. EP/C512804 and EP/C512812. ...

doi:10.1145/1450135.1450182 dblp:conf/codes/OggAY08 fatcat:igqqykj7sfgfdcyyqlfgczogkq

The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token ... at the most likely processor to issue the create instruction. ... The design described in this paper uses a point to point connection between arbiter modules. A delay-insensitive methodology is used giving unbounded delays to both wires and logic gates. ...

doi:10.1016/j.sysarc.2006.10.004 fatcat:7rhkhmginvcnjb74qu5j5cntw4

and frequency subject to workload requirements and S/N conditions. ... This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme; it minimises the interconnect voltage swing ... code (n = 8 redundant bits added to each N = 32-bit word) to detect errors. ...

doi:10.1145/581220.581221 fatcat:xvsjt7znznda5hppaxnk6it5ai

and frequency subject to workload requirements and S/N conditions. ... This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme; it minimises the interconnect voltage swing ... code (n = 8 redundant bits added to each N = 32-bit word) to detect errors. ...

doi:10.1145/581199.581221 fatcat:cbb26dk4qbdqzozrzcmxyydkuy

Delay-insensitive, point-to-point interconnect using m-of-n codes

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An adaptive low-power transmission scheme for on-chip networks

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