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Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

Deming Chen, Jason Cong
2004 Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04  
This paper presents a delay optimal FPGA clustering algorithm targeting low power.  ...  We assume that the configurable logic blocks of the FPGA can be programmed using either a high supply voltage (high-Vdd) or a low supply voltage (low-Vdd).  ...  CONCLUSIONS AND FUTURE WORK We presented a delay optimal low-power clustering algorithm DVpack for FPGA architecture with a dual-Vdd setting.  ... 
doi:10.1145/1013235.1013259 dblp:conf/islped/ChenC04 fatcat:mvujja7krnaffeatgk5walfh2a

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Fei Li, Yan Lin, Lei He, Jason Cong
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
Therefore, programmability of supply voltage is needed to achieve significant power saving for dual-Vdd FPGAs.  ...  We design FPGA circuits with dual-Vdd/dual-Vt to effectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits.  ...  Figure 6 : 6 A level converter circuit with single supply voltage. Figure 7 : 7 A FPGA with cluster-based logic blocks and island style routing structures.  ... 
doi:10.1145/968280.968288 dblp:conf/fpga/LiLHC04 fatcat:6o3552pw2rfrxotftrcatks4ci

A Dual-V DD Low Power FPGA Architecture [chapter]

A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, T. Tuan
2004 Lecture Notes in Computer Science  
In this work, we propose a programmable dual-VDD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-VDD to non-critical  ...  Our experimental results show that reducing the supply voltage selectively to the non-critical paths provides significant power savings with minimal impact on performance.  ...  [5] presents a cut enumeration algorithm targeting low power technology mapping for FPGA architectures with dual supply voltages.  ... 
doi:10.1007/978-3-540-30117-2_17 fatcat:gvj5w5q4nvfxvaz6bx7qkuk2fi

Evaluation of dual VDD fabrics for low power FPGAs

Rajarshi Mukherjee, Seda Ogrenci Memik
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
with 17% area/delay product penalty and 30% power gain is possible with as low as 6% area/delay product penalty for different voltage island configurations.  ...  Power efficiency is becoming an increasingly important design aspect for FPGAs.  ...  Li et al. first reported power reduction using dual supply /dual threshold voltage for pre-defined FPGA fabrics [13] .  ... 
doi:10.1145/1120725.1121033 dblp:conf/aspdac/MukherjeeM05 fatcat:z4e3uvltwvba7de463hcno6nou

FPGA power reduction using configurable dual-Vdd

Fei Li, Yan Lin, Lei He
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
Compared to single-Vdd FPGAs with optimized Vdd level for the same target clock frequency, configurable dual-Vdd FPGAs with full and partial supply programmability for logic blocks reduce logic power by  ...  Power optimization is of growing importance for FPGAs in nanometer technologies.  ...  Compared to single-Vdd FPGAs with Vdd level optimized for the same target clock frequency, dual-Vdd FPGAs with full supply programmability for logic blocks reduce logic power by 35.50% and increase logic  ... 
doi:10.1145/996566.996767 dblp:conf/dac/LiLH04 fatcat:thamhwhnofawfa24b3u7v3lf4e

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng
2010 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization.  ...  Index Terms-Dual-supply voltages, field-programmable gate array (FPGA), power optimization, technology mapping.  ...  Specifically, we will work on technology mapping and clustering for FPGA circuits using dual supply voltages.  ... 
doi:10.1109/tcad.2010.2061770 fatcat:qoji4fsvnffprak4kqiccjjrwq

A low-power FPGA based on self-adaptive multi-voltage control

Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
2013 2013 International SoC Design Conference (ISOCC)  
This paper presents a low-power FPGA that the supply voltage of each logic block autonomously changes to suit their deadlines.  ...  When a low supply voltage does not violate the deadline, the supply voltage of the logic block is autonomously switched to the low voltage.  ...  ACKNOWLEDGMENT This work is supported by JSPS KAKENHI Grant Number 25·6949, VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with STARC, e-Shuttle Inc., Fujitsu Ltd., Cadence  ... 
doi:10.1109/isocc.2013.6863962 fatcat:wx4utpvwinh3dld7nlioyws6qi

Field Programmability of Supply Voltages for FPGA Power Reduction

Fei Li, Yan Lin, Lei He
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Power reduction is of growing importance for fieldprogrammable gate arrays (FPGAs). In this paper, we apply programmable supply voltage (Vdd) to reduce FPGA power.  ...  Index Terms-Dual Vdd, field-programmable gate array (FPGA) architecture, power reduction, supply-voltage programmability.  ...  TABLE I LEAKAGE I POWER FOR A P-BLOCK CONTAINING ONE FOUR-INPUT LUT Fig. 5. Level-converter circuit with single supply voltage.  ... 
doi:10.1109/tcad.2006.884848 fatcat:vtj3hwgstvcwrfhm7547b5fbqe

Reduction of Power Consumption in FPGAs - An Overview

Naresh Grover, M. K.Soni
2012 International Journal of Information Engineering and Electronic Business  
FPGAs the platform of choice for implementing digital circuits.  ...  It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.  ...  In a dual-VDD IC, circuitry that is not delay-critical is powered by the lower supply voltage; delay-critical circuitry is powered by the higher supply.  ... 
doi:10.5815/ijieeb.2012.05.07 fatcat:7leaijfferarfoenxtdk2mlahq

Low-power technology mapping for FPGA architectures with dual supply voltages

Deming Chen, Jason Cong, Fei Li, Lei He
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization.  ...  In addition, we investigate the best low-Vdd/high-Vdd ratio for the largest power reduction among several dual-Vdd combinations.  ...  Jason Anderson of University of Toronto for providing mapping results and associated benchmarks.  ... 
doi:10.1145/968280.968297 dblp:conf/fpga/ChenCLH04 fatcat:ufr7afbbd5attevh6c6ejzngtm

Circuits and architectures for field programmable gate array with configurable supply voltage

Y. Lin, Fei Li, Lei He
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Field programmable gate arrays (FPGAs) with supply voltage (Vdd) programmability have been proposed recently to reduce FPGA power, where the Vdd-level can be customized for FPGA circuit elements and unused  ...  Index Terms-Digital integrated circuits, field programmable gate arrays (FPGAs), power supplies.  ...  Alternatively, dual-Vdd applies high supply voltage (VddH) to the logic on the critical path and low supply voltage (VddL) to the logic not on the critical path.  ... 
doi:10.1109/tvlsi.2005.857180 fatcat:zpjhtfstb5d7fjnoakanby7dwq

95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping

Canh Tran, Hiroshi Kawaguchi, Takayasu Sakurai
2005 2005 IEEE Asian Solid-State Circuits Conference  
The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem.  ...  Low-power FPGA architecture is proposed based on fine-grained V DD control scheme called micro-V DD -hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V DD is shared.  ...  To compare the leakage power of the proposed FPGA with the conventional FPGA, simulations using 90nm CMOS technology with dual V TH are carried out.  ... 
doi:10.1109/asscc.2005.251687 fatcat:sgep6u45h5fmhbrfi3shoafope

Power-Driven Design Partitioning [chapter]

Rajarshi Mukherjee, Seda Ogrenci Memik
2004 Lecture Notes in Computer Science  
Further we did constrained placement of the clusters into predefined V dd high and V dd low regions for a single FPGA.  ...  Our power-driven partitioner creates clusters within a design such that within individual clusters, power consumption can be improved via voltage scaling.  ...  In addition, Chen et al. reported recent results on the feasibility of dual supply voltage FPGA fabrics [14] , [15] .  ... 
doi:10.1007/978-3-540-30117-2_75 fatcat:oamclpzjrnbczaaaxvg7qb55wq

Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems

Michael Lueders, Bjoern Eversmann, Johannes Gerber, Korbinian Huber, Ruediger Kuhn, Michael Zwerg, Doris Schmitt-Landsiedel, Ralf Brederlow
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Field Programmab le Gate Arrays (FPGAs) are widely used for imp lementation of dig ital system design due to their flexibility, low time-to-market, growing density and speed.  ...  After reviewing latest research work on power reduction in FPGA we examined that using Dual VT and fine-grained VDD static power reduces upto 64% and 95% respectively.  ...  A steep sub-threshold transistor allows us to operate at very low threshold voltages with ultra low leakage and low supply voltages (V DD ).  ... 
doi:10.1109/tvlsi.2013.2290083 fatcat:j2wsmzogunazpbwdx3wicplemu

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping

C. Q. TRAN
2006 IEICE transactions on electronics  
A test chip was fabricated using a 0.35-µm CMOS technology, together with the conventional fixed-V DD FPGA for comparison.  ...  A low-power level shifter that has less contention is also proposed for lowswing inter-block signals.  ...  Acknowledgments Valuable discussions with Mr. K. Mashiko, A. Hashiguchi, Y. Ueda, M. Nomura, H. Yamamoto from Semiconductor Technology Academic Research Center (STARC) and M.  ... 
doi:10.1093/ietele/e89-c.3.280 fatcat:7rnccessrff7ta3psclq7skeau
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