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Delay minimization and technology mapping of two-level structures and implementation using clock-delayed domino logic

Jovanka Ciric, Gin Yee, Carl Sechen
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
We take advantage of CD domino's high-speed, large fan-in NOR and OR gates to increase the speed of a circuit by partial collapsing.  ...  The results on eight combinational MCNC benchmark circuits show an average speed improvement of 89% for CD domino with TLS, compared to static CMOS implementations generated by Synopsys.  ...  Acknowledgements We are grateful for the financial support provided by the SRC, CDADIC, National Science Foundation and Sun Microsystems. We would like to acknowledge the help of Tyler Thorp.  ... 
doi:10.1145/343647.343781 fatcat:b73ielprwneilicxcqctrrrzzq

Power-aware FPGA logic synthesis using binary decision diagrams

Kevin Oo Tinmaung, David Howland, Russell Tessier
2007 Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays - FPGA '07  
Our approach achieves an average energy reduction of 13% for Altera Cyclone II devices versus synthesis with SIS-based algebraic optimization at the cost of 11% average circuit performance if performance-optimal  ...  If technology mapping is tuned to achieve the same average delay for both SIS and BDD-based flows, a 3% average energy reduction is achieved by our new synthesis approach.  ...  ACKNOWLEDGMENTS This work was funded by a grant from Altera Corporation. We thank Julien Lamoureux from the University of British Columbia for providing the EMap software.  ... 
doi:10.1145/1216919.1216945 dblp:conf/fpga/TinmaungHT07 fatcat:j6pavdhbfze7nadakn3bvuxnuu

BDD-based logic synthesis for LUT-based FPGAs

Navin Vemuri, Priyank Kalla, Russell Tessier
2002 ACM Transactions on Design Automation of Electronic Systems  
To induce good decompositions, a maximum fanout free cone (MFFC) based partial clustering and collapsing technique is used.  ...  As a post-processing step, a performance-driven re-synthesis phase is performed to alleviate increased delay caused by excessive logic sharing.  ...  Maciej Ciesielski (Univ of Massachusetts, Amherst) and Congguang Yang (Chameleon Systems) for providing their logic synthesis tool, BDS, for use in our work.  ... 
doi:10.1145/605440.605442 fatcat:j6vwy7weynfyhairj24cmq3xxq

Technology mapping issues for an FPGA with lookup tables and PLA-like blocks

Alireza Kaviani, Stephen Brown
2000 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00  
The technology mapping algorithms partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of LUTs and PLA-like blocks.  ...  Instead, to illustrate the importance of this problem we use our algorithms to investigate the benefits provided by a PLD architecture with both LUTs and PLA-like blocks compared to a traditional LUT-based  ...  After optimization by Synopsys, we collapse the circuits to a given depth and then reduce their area.  ... 
doi:10.1145/329166.329180 dblp:conf/fpga/KavianiB00 fatcat:36di7wxan5ecdiiexbrkzvzyfa

Timing-driven logic bi-decomposition

J. Cortadella
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
It combines two strategies: logic bi-decomposition of Boolean functions and tree-height reduction of Boolean expressions.  ...  An approach for logic decomposition that produces circuits with reduced logic depth is presented.  ...  In the future, we foresee combining partial collapsing and decomposition to manage much larger examples.  ... 
doi:10.1109/tcad.2003.811447 fatcat:bpejh75tevctfkrr5c4qvoyqeu

Performance-driven mapping for cpld architectures

Deming Chen, J. Cong, M. Ercegovac, Zhijun Huang
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
With a relatively small area overhead, PLAmap reduces circuit depth by 50% compared to TEMPLA and reduces circuit delay by 48% compared to MAX + PLUS II v9.6.  ...  We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells.  ...  If each cluster is feasible and transformed into a PLA, we can simply approximate the circuit delay by using a unit PLA-delay model.  ... 
doi:10.1109/tcad.2003.818120 fatcat:yywqxrwjcrdjdm5tlzyof57c2e

Performance-driven mapping for CPLD architectures

Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
2001 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays - FPGA '01  
With a relatively small area overhead, PLAmap reduces circuit depth by 50% compared to TEMPLA and reduces circuit delay by 48% compared to MAX + PLUS II v9.6.  ...  We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells.  ...  If each cluster is feasible and transformed into a PLA, we can simply approximate the circuit delay by using a unit PLA-delay model.  ... 
doi:10.1145/360276.360296 dblp:conf/fpga/ChenCEH01 fatcat:ofm6nzuy4ze4pkr6mfe4rs7guq

The hybrid field-programmable architecture

A. Kaviani, S. Brown
1999 IEEE Design & Test of Computers  
Their main strengths are very high logic capacity-in the range of hundreds of thousands of equivalent logic gates-and good speed-performance-up to 50-MHz system clock rates.  ...  The authors propose a new architecture that combines two existing technologies: lookuptable-based FPGAs and complex programmable logic devices based on PLA-like blocks.  ...  It consists of a series of partial collapsing and factoring (decomposition) operations.  ... 
doi:10.1109/54.765206 fatcat:irwicflg3zghrfqyct635xm2i4

Technology mapping algorithms for hybrid fpgas containing lookup tables and plas

S. Krishnamoorthy, R. Tessier
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Present commercial tools, which target these hybrid devices, require hand partitioning of user designs to isolate logic for each type of logic resource.  ...  It is shown that when timing constrained, hybridmap reduces LUT consumption for Apex20KE devices (Altera Corporation 1999) by 8% and when unconstrained by 14% by migrating logic from LUTs to Pterm structures  ...  Kaviani for discussions regarding the hybrid technology mapping problem and for providing the circuits that were previously used in [31] . Thanks are due to E.  ... 
doi:10.1109/tcad.2003.810743 fatcat:vp4jmm4pzresfj7gtmvysfshj4

Circuit clustering for delay minimization under area and pin constraints

H.H. Yang, D.F. Wong
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We allow duplication of logic gates as it would reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering.  ...  We tested our algorithm on a set of benchmark circuits and consistently obtained optimal or near-optimal delays.  ...  We allow duplication of logic gates as it would reduce circuit delay. Circuit partitioning with duplication of logic gates is also referred to as circuit clustering.  ... 
doi:10.1109/43.658566 fatcat:mfs4np76qbbaho7u2zzakzewc4

Synthesis method for field programmable gate arrays

A. Sangiovanni-Vincentelli, A. El Gamal, J. Rose
1993 Proceedings of the IEEE  
The emphasis is on tools which attempt to minimize the area of the combinational logic part of a design since little work has been done on optimizing performance or routability, or on synthesis of the  ...  The three most popular types of FPGA architectures are considered, namely those using logic blocks based on lookuptables, multiplexers and wide AND/OR arrays.  ...  This work is partially supported by DARPA under contract numbers J-FBI-90-073 (for the first author) and J-FBI-89-101 (for the second author).  ... 
doi:10.1109/5.231344 fatcat:gydi5y4v2rab5add3fr2q7myta

Combining Technology Mapping With Layout

Massoud Pedram, Narasimha Bhat, Ernest S. Kuh
1997 VLSI design (Print)  
itself is guided by the evolving logic structure and accurate path-based delay traces.  ...  The premise of this paper is that by increasing the interaction between logic synthesis and physical design, circuits with smaller area and interconnection length, and improved performance and routability  ...  Performance optimization logic restructuring operations (e.g., depth reduction [13] , partial collapse and resynthesis along the critical paths [25] , logic clustering and partial collapse [26] , etc  ... 
doi:10.1155/1997/73654 fatcat:6d3j563congtpeabr4is64izva

BDD-based circuit restructuring for reducing dynamic power

Quang Dinh, Deming Chen, Martin D. F. Wong
2010 2010 IEEE International Conference on Computer Design  
We then use ILP formulation to select the optimal set of control signals for the circuit.  ...  Clock gating is a dynamic power saving technique that can freeze some flip-flops and prevent portion of the circuit from unneeded switching.  ...  ACKNOWLEDGEMENTS This work is partially supported by NFS grants CCF-0746608, CCF-0701821, and SHF-1017516.  ... 
doi:10.1109/iccd.2010.5647524 dblp:conf/iccd/DinhCW10 fatcat:pzfbdtkpk5d5pmnxswuqi5ku3m

A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

Christian Legl, Bernd Wurth, Klaus Eckl
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
As the core of the approach, we have developed a powerful functional decomposition algorithm. The impact of decomposition is enhanced by a preceding collapsing step.  ...  The procedure optimizes the variable partition for each bound set size by iteratively exchanging variables between bound set and free set, and finally selects a good bound set size.  ...  Antreich and Dr. Ulf Schlichtmann for many valuable discussions.  ... 
doi:10.1145/240518.240657 dblp:conf/dac/LeglWE96 fatcat:x6nnmh4r4faubn6if5svyislue

Exploiting signal flow and logic dependency in standard cell placement

Jason Cong, Dongmin Xu
1995 Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95  
In this paper, we exploit the use of signal flow and logic dependency in standard cell placement by using the maximum fanout-free cone (MFFC) decomposition technique.  ...  We also developed a placement algorithm, named MFFC-TW, which first clusters the circuit based on MFFC decomposition and then feeds the clustered circuit to the Timberwolf6.0 placement package.  ...  Acknowledgments This work was partially supported by ARPA/CSTO under Contract J-FBI-93-112 for Computer Aided Design of High Performance Wireless Networked Systems.  ... 
doi:10.1145/224818.224931 dblp:conf/aspdac/CongX95 fatcat:b5q6c2iv6bgb3pssijvuxg4mme
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