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Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects

M. Yilmaz, K. Chakrabarty, M. Tehranipoor
2008 2008 IEEE International Test Conference  
For the same pattern count, the proposed pattern-grading and pattern-selection method is more effective than a commercial timing-aware ATPG tool for SDDs, and requires considerably less CPU time.  ...  We present a layout-aware output deviations metric that can easily handle interconnect delay variations.  ...  If highly effective test patterns are applied first in a reordered test set, defective chips will fail earlier, reducing test application time in an abort-at-firstfail environment.  ... 
doi:10.1109/test.2008.4700627 dblp:conf/itc/YilmazCT08 fatcat:yrzrhjpwazgubickturnfqxnqy

Defect Aware Test Patterns

Huaxing Tang, Gang Chen, S.M. Reddy, Chen Wang, J. Rajski, I. Pomeranz
Design, Automation and Test in Europe  
A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns have greater ability to detect un-modeled defects.  ...  Experimental results on several industrial designs show the effectiveness of defect aware tests.  ...  We use 4-way bridging faults as surrogates for un-modeled defects in evaluating the method proposed in this work to generate defect aware tests.  ... 
doi:10.1109/date.2005.110 dblp:conf/date/TangCRWRP05 fatcat:az4xbdre2febjhdd7eote2ad7i

A Method for Selecting Test Patterns for Defect-Aware Test by using 0-1 Integer Linear Program

Hiroshi SHIDA, Yoshinobu HIGAMI, Hirohisa AMAN, Hiroshi TAKAHASHI, Kewal K. SALUJA
2014 The Journal of Reliability Association of Japan  
We also formulate the method for selecting the test patterns from the N − detection test set based on the defect detection probability as a O − 1 integer linear program .  ...  number of test pattern counts is the problem .  ...  欠 陥,欠 陥検 出 向 け テ ス トパ タ ー ン ,欠 陥検 出確 率 ,0 − 1 整 数 計画 問題 を 利用 した テ ス ト パ タ ー ン 選 択 法 defectdefectaware test patterndefect detection probability, method for selecting test patterns by using O − 1  ... 
doi:10.11348/reajshinrai.36.8_501 fatcat:dowvubwqu5efdcqinhpn4j3vk4

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, Mohammad Tehranipoor
2010 2010 19th IEEE Asian Test Symposium  
For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon.  ...  ATPG, but only with a significantly small number of test patterns and in significantly small run time. .  ...  Timing-aware patterns do not require test application at higher-than-system speed, although if applied can also detect some reliability defects.  ... 
doi:10.1109/ats.2010.59 dblp:conf/ats/GoelCYPT10 fatcat:leojyajbe5er3bjxj6uaowvy4e

Test Pattern Ordering and Selection for High Quality Test Set under Constraints

Michiko INOUE, Akira TAKETANI, Tomokazu YONEDA, Hideo FUJIWARA
2012 IEICE transactions on information and systems  
The proposed method efficiently orders test patterns with minimal usage of time-consuming timing-aware fault simulation.  ...  Test pattern ordering gives a practical solution to reduce test cost, where test patterns are ordered so that more defects can be detected as early as possible.  ...  That means each test patterns generated by timing-aware ATPG detect more amount of defects than n-detect ATPGs.  ... 
doi:10.1587/transinf.e95.d.3001 fatcat:l4xof5r3gvhs3jsnpahxfpnp2y

Cell-Aware Test

Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja Fast
2014 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs  ...  We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million.  ...  This methodology is named cell-aware-test. III. CELL-AWARE TEST METHODOLOGY The CAT methodology consists of two major parts.  ... 
doi:10.1109/tcad.2014.2323216 fatcat:7hc2mziocrgijhyeoakpi2ywze

Scan-Chain Intra-Cell Aware Testing

Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray
2018 IEEE Transactions on Emerging Topics in Computing  
We exploit a commercial intra-cell aware ATPG tool to generate a test pattern set able to detect escaped defects.  ...  If we consider b18, the proposed approach generates about 72% less patterns than the intra-cell aware ATPG (10,170 vs. 49,369 test patterns).  ... 
doi:10.1109/tetc.2016.2624311 fatcat:k7ksqcb5nvgcreg472aqv7bqmu

Test-Pattern Grading and Pattern Selection for Small-Delay Defects

Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2008 Proceedings of the ... IEEE VLSI Test Symposium  
We show that, for the same pattern count, the selected patterns are more effective than timing-aware ATPG for detecting small delay defects caused by resistive shorts, resistive opens, and process variations  ...  The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG).  ...  If highly effective test patterns are applied first in a reordered test set, defective chips will fail earlier, reducing test application time in an abort-at-first-fail environment.  ... 
doi:10.1109/vts.2008.32 dblp:conf/vts/YilmazCT08 fatcat:wdk45eqqszedljtsgslymonkve

Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference

S. Mhamdi, P. Girard, A. Virazel, A. Bosio, A. Ladhar
2021 2021 22nd International Symposium on Quality Electronic Design (ISQED)  
This paper presents a new cell-aware diagnosis flow that can be used to address a specific scenario (test protocol) one may encounter during diagnosis of customer returns.  ...  In this flow, we use a Bayesian classification method to precisely identify defect candidates.  ...  First, cell-aware dynamic test patterns are applied to the failing CUD.  ... 
doi:10.1109/isqed51717.2021.9424337 fatcat:4gkjleyuvzdzteaoguir7tienm

Physically-awareN-detect test pattern selection

Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, R. D. (Shawn) Blanton
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
N -detect test has been shown to have a higher likelihood for detecting defects. However, traditional definitions of Ndetect test do not necessarily exploit the localized characteristics of defects.  ...  Results produced for an industrial test chip demonstrate the effectiveness and practicability of our pattern selection approach.  ...  Another advantage of N -detect test over other defect-oriented models is that existing approaches to automatic test pattern generation (ATPG) can be easily modified to generate N -detect test patterns.  ... 
doi:10.1145/1403375.1403528 fatcat:jerxp3zf4jhpnpj5pj4rhkwkt4

TSV Stress-Aware ATPG for 3D Stacked ICs

Sergej Deutsch, Krishnendu Chakrabarty, Shreepad Panth, Sung Kyu Lim
2012 2012 IEEE 21st Asian Test Symposium  
We therefore conclude that any detrimental impact of TSV stress on pattern effectiveness and test quality can be overcome by using stress-aware models for test generation.  ...  Our results also indicate that we can improve the test quality by using TSV-stress aware cell libraries in a conventional ATPG flow with commercial tools, with negligible impact on pattern count.  ...  With this metric, we can quantitatively estimate the test escape rate due to delay defects and evaluate the increase in test quality if TSV stress-aware circuit models are used for ATPG.  ... 
doi:10.1109/ats.2012.61 dblp:conf/ats/DeutschCPL12 fatcat:2bim4gnufzc4pd26er64ail7w4

Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits

Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor
2010 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We present a test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs).  ...  Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits.  ...  Fig. 10 . 10 Number of defects detected by the selected patterns for dev, dts, the trimmed timing-aware ATPG patterns (ta trimmed), and full set of timing-aware ATPG patterns (ta) (ta is a super-set of  ... 
doi:10.1109/tcad.2010.2043591 fatcat:ekban7eh25bjzkpf67e6cx25cq

Towards Variation-Aware Test Methods

Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter Maxwell
2011 2011 Sixteenth IEEE European Test Symposium  
For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial.  ...  For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial.  ...  Variation-aware fault coverage metrics The first difficulty in variation-aware test is to define when a fault is actually "detected" by a test pattern or a test set, and, consequently, the "fault coverage  ... 
doi:10.1109/ets.2011.51 dblp:conf/ets/PolianBHWM11 fatcat:wdzk6ughijgulh226qblm75kmq

Delay Testing: Improving Test Quality and Avoiding Over-testing

Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
2011 IPSJ Transactions on System LSI Design Methodology  
Most methods of power-aware test generation and noise-aware test generation are based on post-ATPG process such as X-filling that fills X bits in test patterns.  ...  The disadvantages of timing-aware test generation are the increase of test pattern count and runtime of ATPG.  ... 
doi:10.2197/ipsjtsldm.4.117 fatcat:b5mup2ufwjeqnkoa6erenziyju

A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns

S. Mhamdi, P. Girard, A. Virazel, A. Bosio, A. Ladhar
2020 2020 IEEE International Test Conference (ITC)  
By using a Naive Bayes classifier to accurately identify defect candidates, the proposed flow indistinctly deals with static and dynamic defects that may occur in actual circuits.  ...  Results achieved on benchmark circuits, as well as comparison with a commercial cell-aware diagnosis tool, show the effectiveness of the proposed framework in terms of accuracy and resolution.  ...  Cell-aware delay test sequences generated by a cell-aware ATPG assuming a Launch-On-Capture (LOC) testing scheme were used in this work.  ... 
doi:10.1109/itc44778.2020.9325246 fatcat:dft5pyekurhwdkaullstiqjqxi
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