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DeepAttest

Huili Chen, Cheng Fu, Bita Darvish Rouhani, Jishen Zhao, Farinaz Koushanfar
2019 Proceedings of the 46th International Symposium on Computer Architecture - ISCA '19  
Emerging hardware architectures for Deep Neural Networks (DNNs) are being commercialized and considered as the hardwarelevel Intellectual Property (IP) of the device providers.  ...  To facilitate the deployment, we provide a high-level API of DeepAttest that can be seamlessly integrated into existing deep learning frameworks and TEEs for hardware-level IP protection and usage control  ...  Table 1 : Requirements for an effective on-device attestation technique of deep neural networks.  ... 
doi:10.1145/3307650.3322251 dblp:conf/isca/ChenFRZK19 fatcat:o2oknyg36zht3lxoelu7dasv2e

Intellectual Property Protection for Deep Learning Models: Taxonomy, Methods, Attacks, and Evaluations [article]

Mingfu Xue, Yushu Zhang, Jian Wang, Weiqiang Liu
2021 arXiv   pre-print
To deal with such security threats, a few deep neural networks (DNN) IP protection methods have been proposed in recent years.  ...  This paper attempts to provide a review of the existing DNN IP protection works and also an outlook.  ...  [11] proposed an attestation method for DNN devices (named DeepAttest), so as to provide hardware IP protection for DNN applications.  ... 
arXiv:2011.13564v2 fatcat:lbts5q52b5axzlmuitb2u62dfa

Real, Forged or Deep Fake? Enabling the Ground Truth on the Internet

Mohammad A. Hoque, Md Sadek Ferdous, Mohsin Khan, Sasu Tarkoma
2021 IEEE Access  
This paper further emphasizes that we desperately need socio-technological solutions that empower end users with the right tools to make an informed moral decision while producing, uploading, and sharing  ...  The proliferation of smartphones and mobile communication has enabled users to capture images or videos and share them immediately on social networking and messaging platforms.  ...  DeepAttest [66] is an effort where the hardware specifically attests the output from the emerging hardware, such as GPU, FPGA, and ASIC, for the deep neural networks.  ... 
doi:10.1109/access.2021.3131517 fatcat:lqwguwepjfbqjc7puzvecld5eq