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A Simulation Study of Decoupled Architecture Computers

Smith, Weiss, Pang
1986 IEEE transactions on computers  
Several decoupled architectures have been proposed, and they all have two characteristics in common: 1) they have two separate sets of instructions, one for accessing memory and one for performing function  ...  We first describe a decoupled architecture based on the CRAY-1 scalar architecture. The sensitivity to memory access delays are studied by varying memory access time over a wide range o,f yalues.  ...  Fig. 7(b) shows the speedups for the decoupled computer as compared to the original CRAY-1.  ... 
doi:10.1109/tc.1986.1676820 fatcat:eosp2gquaff3bf73znsx6iwtw4

Multithreading decoupled architectures for complexity-effective general purpose computing

Michael Sung, Ronny Krashinsky, Krste Asanović
2001 SIGARCH Computer Architecture News  
Decoupled architectures have not traditionally been used in the context of general purpose computing because of their inability to tolerate control-intensive code that exists across a wide range of applications  ...  A proposal for a multithreaded decoupled control/access/execute architecture is presented as a platform for achieving high performance on general purpose workloads.  ...  This sort of speculation is a natural fit for the decoupled architectures because all the memory addresses are put in queues.  ... 
doi:10.1145/563647.563658 fatcat:fjmdpove5ravhclvctbfurz6im

MediaBreeze

Deependra Talla, Lizy K. John
2001 SIGARCH Computer Architecture News  
In this paper, we present an architecture that decouples the useful/true computations from the overhead/supporting instructions in media applications.  ...  Decoupled architectures are fine-grain processors that partition the memory access and execute functions in a computer program and exploit the parallelism between the two functions.  ...  Figure 1 . 1 A Typical Decoupled Architecture • Data station: The data station acts as a register file for the SIMD computation.  ... 
doi:10.1145/563647.563659 fatcat:7h53vlbrxncrnbqmfzrtxmqcti

Hardware support for software controlled multithreading

Aqeel Mahesri, Nicholas J. Wang, Sanjay J. Patel
2007 SIGARCH Computer Architecture News  
This prevents non-critical instructions from competing with critical instructions for processor resources, allowing the critical thread (and thus the workload) to complete faster.  ...  The master threads generally consist of performance critical instructions that can prefetch data, compute critical control descisions, or compute performance critical dataflow slices.  ...  DECOUPLING IMPLEMENTATION The NXA architecture provides a target for decoupled programming.  ... 
doi:10.1145/1241601.1241606 fatcat:aabcvs7w5vgw3o3bqtmgx3hdpa

A decoupled data-driven architecture with vectors and macro actors [chapter]

Paraskevas Evripidou, Jean-Luc Gaudiot
1990 Lecture Notes in Computer Science  
A graph unit executes all graph operations and a computation unit executes all computation operations.  ...  A block-scheduling technique for extracting more parallelism from sequential constructs is incorporated in the decoupled architecture.  ...  In the decoupled architecture, the graph unit executes all graph operations (determination of executability) and the computation unit executes all computation operations (code fetching and execution).  ... 
doi:10.1007/3-540-53065-7_86 fatcat:ghn3mkgihbfr5d3ddpqulp6pza

The effectiveness of decoupling

Peter L. Bird, Alasdair Rawsthorne, Nigel P. Topham
1993 Proceedings of the 7th international conference on Supercomputing - ICS '93  
This paper examines the effectiveness of decoupling as an optimization technique for high-performance computer architectures.  ...  Abstract This paper examines the effectiveness of decoupling as an optimization technique for high-performance computer architectures.  ...  Subroutine PRNSE2 One subroutine which appears to cause problems for a decoupled architecture is PRNSE2.  ... 
doi:10.1145/165939.165952 dblp:conf/ics/BirdRT93 fatcat:ohmaaj7hcrh2vk3bavwb2ofg2a

Improving latency tolerance of multithreading through decoupling

J.-M. Parcerisa, A. Gonzalez
2001 IEEE transactions on computers  
Our study shows that, by adding decoupling to a multithreaded architecture, fewer threads are needed to achieve maximum throughput.  ...  for future growth in issue-width and clock speed.  ...  ACKNOWLEDGMENTS The authors thank the anonymous referees for their valuable comments.  ... 
doi:10.1109/12.956093 fatcat:id5zuvaajfcildot55nuokrb4m

Decoupled access/execute computer architectures

James E. Smith
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
An architecture for high-performance scalar computation is proposed and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution.  ...  This allows known compilation and programming techniques to be used. Finally, the problem of deadlock in a decoupled system is discussed, and a deadlock prevention method is given.  ...  The A-processor performs all operations necessary for transferring data to and from main memory. That is, it does all address computation and performs all memory read and write requests.  ... 
doi:10.1145/285930.285982 dblp:conf/isca/Smith98d fatcat:rerg34mrpjecpe32m74foppnwm

Decoupled access/execute computer architectures

James E. Smith
1984 ACM Transactions on Computer Systems  
An architecture for high-performance scalar computation is proposed and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution.  ...  This allows known compilation and programming techniques to be used. Finally, the problem of deadlock in a decoupled system is discussed, and a deadlock prevention method is given.  ...  The A-processor performs all operations necessary for transferring data to and from main memory. That is, it does all address computation and performs all memory read and write requests.  ... 
doi:10.1145/357401.357403 fatcat:bldhhclgifhjdeza2a2bgsxvne

Decoupled access/execute computer architectures

James E. Smith
1982 SIGARCH Computer Architecture News  
An architecture for high-performance scalar computation is proposed and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution.  ...  This allows known compilation and programming techniques to be used. Finally, the problem of deadlock in a decoupled system is discussed, and a deadlock prevention method is given.  ...  The A-processor performs all operations necessary for transferring data to and from main memory. That is, it does all address computation and performs all memory read and write requests.  ... 
doi:10.1145/1067649.801719 fatcat:rs7imhyh3fd53bzkn27kskr5cq

On-Chip Nanoscale Capacitor Decoupling Architectures for Hardware Security

Matthew Mayhew, Radu Muresan
2014 IEEE Transactions on Emerging Topics in Computing  
All architectures were found to resist the correlation PAA at the power supply, with the more complex architectures also offering protection against invasive attacks.  ...  Specifically, three circuit level architectures called partial decoupling architecture, full decoupling architecture, and randomized switch box architecture are developed and analyzed.  ...  It was also the only architecture to prevent the CPA at all capacitor terminals. With this in mind, the partial decoupling architecture is likely best suited for systems with strict area constraints.  ... 
doi:10.1109/tetc.2014.2303934 fatcat:vhkmzkgmafc6rlruysmrlswlci

A Decoupled Health Software Architecture using Microservices and OpenEHR Archetypes

Marcio Alexandre, Valéria Cesário, André Magno, Paulo Caetano
2020 International Journal of Computer Applications  
To address this issue in the healthcare domain, a Decoupled Health Software Architecture (DHSA) is proposed in this paper.  ...  For assessing, a legacy software used in Brazilian hospitals is migrated to the DHSA. A comparison is performed between three tools (MARCIA, Template4EHR, and EhrScape).  ...  Coupled and Decoupled Architecture For decades, the use of software architectures whose components are interconnected and interdependent (i.e., coupled) is referred to as monolithic architecture.  ... 
doi:10.5120/ijca2020920302 fatcat:wwg5i6rkmrbtncsmyu3looy6fi

Performance of the decoupled ACRI-1 architecture: The perfect club [chapter]

Nigel Topham, Kenneth McDougall
1995 Lecture Notes in Computer Science  
This paper examines the performance potential of decoupled computer architectures on real-world codes, and includes the rst performance bounds calculations to be published for the highly-decoupled ACRI  ...  -1 computer architecture.  ...  The authors are indebted to Peter Bird and Alasdair Rawsthorne for their original work on the ACRI-1 architecture.  ... 
doi:10.1007/bfb0046669 fatcat:juq7kphb3jfb7kf64ddy7wosmq

Boosting mobile GPU performance with a decoupled access/execute fragment processor

José-María Arnau, Joan-Manuel Parcerisa, Polychronis Xekalakis
2012 SIGARCH Computer Architecture News  
Furthermore, we significantly reduce bandwidth usage in the decoupled architecture by exploiting inter-core data sharing.  ...  For a Tegra like system, we found that if no threading is utilized to hide the latency, the performance hit for a set of 3D Games for the Android is 140%.  ...  More specifically, the proposed scheme uses specifically designed queues to decouple the memory accesses required for bringing all the pixel and texture data from the computations that have to be performed  ... 
doi:10.1145/2366231.2337169 fatcat:f7j676py7jhehcl55u2v2k3b5u

Boosting mobile GPU performance with a decoupled access/execute fragment processor

Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychronis Xekalakis
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
Furthermore, we significantly reduce bandwidth usage in the decoupled architecture by exploiting inter-core data sharing.  ...  For a Tegra like system, we found that if no threading is utilized to hide the latency, the performance hit for a set of 3D Games for the Android is 140%.  ...  More specifically, the proposed scheme uses specifically designed queues to decouple the memory accesses required for bringing all the pixel and texture data from the computations that have to be performed  ... 
doi:10.1109/isca.2012.6237008 dblp:conf/isca/ArnauPX12 fatcat:wu7qgj5rqnh2rhftcvo5xdenge
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