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Decomposition in Asynchronous Circuit Design [chapter]

Walter Vogler, Ralf Wollowski
<span title="">2002</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
È {l} t 1 t 2 p2 l t p1 t 2 l t 1 l p2 l(t 1 ) Î In È {l} t p1 t 2 t 1 p2 l t t 2 p1 l t 1 ÙÖ ÈÖÓÓ ××ÙÑ ÓÒØÖ Ø ÓÒ Ó Ø × ÔÔÐ ØÓ Ò Ö ×ÙÐØ× Ò ¸ Ö ×Ôº ××ÙÑ ÙÖØ Ö Ø Ø × Ò Ò Ð × ÑÙÐ Ø ÓÒ ÓÖ AE Ò ´ µ ¾Á º Ï  ...  ÓÛ× Û Ø Û Ò ´ µ Ò ´ µ Ó ¬Ò Ø ÓÒ º¾ ÓÖ Ò ÓÙÖ ÔÔÖÓ º Ä ÑÑ º ÓÒØÖ Ø ÓÒ ÔÔÐ ØÓ ×ÓÑ Ñ Ñ Ö Ó Ñ ÐÝ ´ µ ¾Á Ø Ø × Ø ×¬ × ´ µ Ò ´ µ Ó ¬Ò Ø ÓÒ º¾ ÔÖ × ÖÚ × Ò Ð ÓÖÖ ØÒ ×× ÛºÖºØº AEº ¾¼ (a) (b) p2 l t p1 l(t 1 ) Î In  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-36190-1_5">doi:10.1007/3-540-36190-1_5</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/hx32ilyumze5pnvcyezkkh64ni">fatcat:hx32ilyumze5pnvcyezkkh64ni</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170921215048/http://opus.bibliothek.uni-augsburg.de/opus4/frontdoor/deliver/index/docId/196/file/TB_2002_05.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/05/38/05386b115b8f8492ddb2f81146498b0877db0220.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-36190-1_5"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

An FPGA for implementing asynchronous circuits

S. Hauck, S. Burns, G. Borriello, C. Ebeling
<span title="">1994</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hkpx3vsnhrfb7jh6hlwads7olq" style="color: black;">IEEE Design &amp; Test of Computers</a> </i> &nbsp;
Montage can be used to realize asynchronous interface circuits or to prototype complete asynchronous systems, thus bringing the benefits of rapid prototyping to asynchronous design.  ...  Field-programmable gate arrays are a dominant implementation medium for digital circuits, especially for glue logic. Unfortunately, they do not support asynchronous circuits.  ...  Gaetano Borriello and Carl Ebeling were supported in part by NSF Presidential Young Investigator Awards. Steven Burns was supported in part by an NSF Young Investigator Award.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.1994.303848">doi:10.1109/mdt.1994.303848</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/idjq6igtizhjvdrny2bq777izy">fatcat:idjq6igtizhjvdrny2bq777izy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20030403152230/http://www.ee.washington.edu:80/people/faculty/hauck/publications/MontageJ.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/09/42/0942594e7e3726a5e75f0527da141a1916029833.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.1994.303848"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Page 1361 of Mathematical Reviews Vol. , Issue 82c [page]

<span title="">1982</span> <i title="American Mathematical Society"> <a target="_blank" rel="noopener" href="https://archive.org/details/pub_mathematical-reviews" style="color: black;">Mathematical Reviews </a> </i> &nbsp;
When synthesizing asynchronous logic circuits, the problem of decomposition is usually solved under the assumption of “permissible” decomposition, i.e. a decomposition which does not lead to an undesirable  ...  ISBN 0-444-41929-2 In designing an electronic circuit, the effect on circuit performances of changes in one or more component values in the circuit is referred to as sensitivity.  ... 
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An EDA tool for implementation of low power and secure crypto-chips

Behnam Ghavami, Hossein Pedram, Mehrdad Najibi
<span title="">2009</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fj5ycmjsdvfz7njycwowhlfiwq" style="color: black;">Computers &amp; electrical engineering</a> </i> &nbsp;
to the existing data driven decomposition asynchronous synthesis method.  ...  In this paper, a fully automated secure design flow and a set of secure library cells resistant to power analysis and fault injection attacks are introduced for quasi delay insensitive asynchronous circuits  ...  Section 3, introduces the asynchronous design and some benefits of using asynchronous circuits in secure hardware. Section 4presents a synthesis tool for QDI asynchronous circuits.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/j.compeleceng.2008.06.014">doi:10.1016/j.compeleceng.2008.06.014</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3bjrexmnbvbilme54efiw64hni">fatcat:3bjrexmnbvbilme54efiw64hni</a> </span>
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Logic decomposition of speed-independent circuits

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A. Yakovlev
<span title="">1999</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a> </i> &nbsp;
Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits.  ...  This paper presents a new method for logic decomposition of speed-independent circuits that solves the problem in two major steps: 1) logic decomposition of complex gates and 2) insertion of new signals  ...  On the other hand, asynchronous circuits offer a few advantages over their synchronous counterparts that explain a recent revival of interest in asynchronous design techniques.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.740027">doi:10.1109/5.740027</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/iip5auyd3jbexpfeu7y2ijfgem">fatcat:iip5auyd3jbexpfeu7y2ijfgem</a> </span>
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High-level fault simulation methodology for QDI template-based asynchronous circuits

Behnam Ghavami, Alireza Tajary, Hamid-Reza Zarandi
<span title="">2009</span> <i title="IEEE"> TENCON 2009 - 2009 IEEE Region 10 Conference </i> &nbsp;
Complexity of design and the lack of suitable test methodology are the major obstacles for widespread use of asynchronous circuit in digital circuit design.  ...  Template based synthesis of asynchronous circuits is accepted as an effective way to decrease the complexity of design.  ...  Table 2 shows results of the circuits testing. IX. CONCLUSIONS Complexity of design and testing are the major obstacle for widespread use of asynchronous circuit in digital circuit design.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tencon.2009.5395804">doi:10.1109/tencon.2009.5395804</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/nji65jzatvgmvinpkhu2gv6bn4">fatcat:nji65jzatvgmvinpkhu2gv6bn4</a> </span>
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Critique of "Asynchronous Logic Implementation Based on Factorized DIMS" [article]

P Balasubramanian
<span title="2018-09-23">2018</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
Moreover, the example illustration in the referenced article describes an unsafe logic decomposition which is not suitable for the multi-level synthesis of strong-indication asynchronous circuits.  ...  Further, a logic synthesis method which safely decomposes the DIMS solution to synthesize multi-level strong-indication asynchronous circuits is available in the existing literature, which was neither  ...  Thus, gate orphan(s) are to be avoided in indicating asynchronous circuit designs but this has been casually overlooked and conveniently neglected in [4] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1711.02333v3">arXiv:1711.02333v3</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/cwtf6pajozaqbas4ousljjzvja">fatcat:cwtf6pajozaqbas4ousljjzvja</a> </span>
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MONTAGE: An FPGA for synchronous and asynchronous circuits [chapter]

Scott Hauck, Gaetano Borriello, Steven Burns, Carl Ebeling
<span title="">1993</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
In this paper we describe Montage, a Triptych-based FPGA designed for implementing asynchronous logic and interfacing separately-clocked synchronous circuits.  ...  Asynchronous circuits have different requirements than synchronous circuits, which make standard FPGAs unusable for asynchronous applications.  ...  Acknowledgments This research was funded in part by the Defense Advanced Research Projects Agency under Contract N00014-J-91-4041.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-57091-8_28">doi:10.1007/3-540-57091-8_28</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/s2ohecvzrnhc3fuvzqwpuehh7e">fatcat:s2ohecvzrnhc3fuvzqwpuehh7e</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20050304064626/http://www.ee.washington.edu:80/faculty/hauck/publications/vienna.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/20/3e/203eb48d09be61b7d1ac14e188b2c9447072228a.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-57091-8_28"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Automated synthesis for asynchronous FPGAs

Song Peng, David Fang, John Teifel, Rajit Manohar
<span title="">2005</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/onq43wd7gna3zbic6lchssp6ke" style="color: black;">Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA &#39;05</a> </i> &nbsp;
Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an AFPGA.  ...  We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures.  ...  Asynchronous FPGA design was proposed as a way to combat the problems of clock distribution in FPGAs, as well as to exploit the data-dependent nature of circuit delays by not having to time the circuit  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1046192.1046214">doi:10.1145/1046192.1046214</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/fpga/PengFTM05.html">dblp:conf/fpga/PengFTM05</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/siz6czvw2nfqzpvaxbvqs63sd4">fatcat:siz6czvw2nfqzpvaxbvqs63sd4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20110810224657/http://web.cecs.pdx.edu/~willem/reading_group/peng-async-fpga.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e8/49/e849a592c1625046fec030ae10916ad098266ba0.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1046192.1046214"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Pre-synthesis Optimization for Asynchronous Circuits Using Compiler Techniques [chapter]

Sharareh ZamanZadeh, Mehrdad Najibi, Hossein Pedram
<span title="">2008</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/jyopc6cf5ze5vipjlm4aztcffi" style="color: black;">Communications in Computer and Information Science</a> </i> &nbsp;
The effectiveness of traditional compiler techniques employed in high-level synthesis of synchronous circuits aiming to present a generic code is studied for asynchronous synthesis by considering the special  ...  for asynchronous benchmarks.  ...  Complier based optimization for asynchronous circuits Complier techniques are employed as presynthesis step prior decomposition [12] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-89985-3_141">doi:10.1007/978-3-540-89985-3_141</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/s2mhxxcj4rdaledmuzuzgyfqby">fatcat:s2mhxxcj4rdaledmuzuzgyfqby</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808185652/http://ceit.aut.ac.ir/~pedram/Papers/CSICC%202008%20Pre-synthesis.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/82/91/8291970af082c15f0b8242af02738ce1461b02d3.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-89985-3_141"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation

Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram
<span title="">2007</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/k4pq3zhykrd3hdhey2qhybwinu" style="color: black;">IEEE Computer Society Annual Symposium on VLSI (ISVLSI &#39;07)</a> </i> &nbsp;
In this paper, we present a new efficient methodology for power estimation of QDI Asynchronous circuits at pre-synthesized level.  ...  Power estimation at high-level is performed by simulating the intermediate format of the design. This format consists of concurrent processes.  ...  We concentrate on high-level power estimation of well known type of asynchronous circuits (QDI circuits), because low power consumption is one of the main advantages of asynchronous circuits.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isvlsi.2007.15">doi:10.1109/isvlsi.2007.15</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/isvlsi/NiknahadGNP07.html">dblp:conf/isvlsi/NiknahadGNP07</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sbmzviwwergr5oogt4vd776ueq">fatcat:sbmzviwwergr5oogt4vd776ueq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170829030555/http://ceit.aut.ac.ir/~pedram/Papers/ISVLSI%202007%20Power.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/0f/f4/0ff49bc031ab29b9bcd159de468e2456db5a7067.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isvlsi.2007.15"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Three generations of asynchronous microprocessors

A.J. Martin, M. Nystrom, C.G. Wong
<span title="">2003</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hkpx3vsnhrfb7jh6hlwads7olq" style="color: black;">IEEE Design &amp; Test of Computers</a> </i> &nbsp;
QDI circuits are the most conservative asynchronous circuits in terms of delays.  ...  Quasi Delay-Insensitive Asynchronous Design The asynchronous circuits we use are called quasi delay-insensitive or QDI.  ...  We are very grateful to DARPA for their unfailing support in spite of widespread skepticism towards asynchronous logic.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.2003.1246159">doi:10.1109/mdt.2003.1246159</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/lwsrz6cudng2jhlytgnpcjffqe">fatcat:lwsrz6cudng2jhlytgnpcjffqe</a> </span>
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High-Level Optimizations in Compiling Process Descriptions to Asynchronous Circuits [chapter]

Ganesh Gopalakrishnan, Venkatesh Akella
<span title="">1994</span> <i title="Springer US"> Asynchronous Circuit Design for VLSI Signal Processing </i> &nbsp;
In this paper, we present our views on why asynchronous systems matter.  ...  We then present details of our high level synthesis tool SHILPA that can automatically synthesize asynchronous circuits from descriptions in our concurrent programming language, hopCP.  ...  Asynchronous circuits o er the designer with even more freedom to explore the design space.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-1-4615-2794-7_4">doi:10.1007/978-1-4615-2794-7_4</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/muh7ntgoyzbgxdllmsy57dpqra">fatcat:muh7ntgoyzbgxdllmsy57dpqra</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170922021711/https://static.aminer.org/pdf/PDF/000/281/668/shilpa_a_high_level_synthesis_system_for_self_timed_circuits.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/96/cb/96cb088833e83da0c94939c7cba9e58fd4cf3e0b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-1-4615-2794-7_4"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Efficient Realization of Strongly Indicating Function Blocks

P. Balasubramanian, D. A. Edwards
<span title="">2008</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/k4pq3zhykrd3hdhey2qhybwinu" style="color: black;">2008 IEEE Computer Society Annual Symposium on VLSI</a> </i> &nbsp;
Approximately 3 times reduction in transistor cost has been achieved by the proposed method in comparison with a recent work, based on analysis with benchmarks and widely used digital circuit functionality  ...  In this context, a novel design methodology for realizing non-regenerative logic as a function block, under the discipline of quasi-delayinsensitivity with four-phase handshaking and dualrail encoding,  ...  The vast majority of existing design automation flows target synchronous circuits. Even when asynchronous designs leverage existing tool flows, they introduce large area overheads.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isvlsi.2008.103">doi:10.1109/isvlsi.2008.103</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/isvlsi/BalasubramanianE08.html">dblp:conf/isvlsi/BalasubramanianE08</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/lyw37jzb4zdvjhqlzjfesoll3m">fatcat:lyw37jzb4zdvjhqlzjfesoll3m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170921231612/http://apt.cs.manchester.ac.uk/ftp/pub/apt/papers/Auth_Bala_ISVLSI2008.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c8/7a/c87a34eb71fc29a64a9fae471802a3ce22d569d5.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isvlsi.2008.103"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

High-level optimizations in compiling process descriptions to asynchronous circuits

Ganesh Gopalakrishnan, Venkatesh Akella
<span title="">1994</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/vj6u7whp3begllofw5o3megb64" style="color: black;">Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology</a> </i> &nbsp;
In this paper, we present our views on why asynchronous systems matter.  ...  We then present details of our high level synthesis tool SHILPA that can automatically synthesize asynchronous circuits from descriptions in our concurrent programming language, hopCP.  ...  Asynchronous circuits o er the designer with even more freedom to explore the design space.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/bf02108188">doi:10.1007/bf02108188</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wridtuyjrvdxbdhqezjtgh42lu">fatcat:wridtuyjrvdxbdhqezjtgh42lu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170922021711/https://static.aminer.org/pdf/PDF/000/281/668/shilpa_a_high_level_synthesis_system_for_self_timed_circuits.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/96/cb/96cb088833e83da0c94939c7cba9e58fd4cf3e0b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/bf02108188"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>
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