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A Distributed Frame Buffer within a Window-Oriented High Performance Graphics System [chapter]

Thomas Haaker, Harald Selzer, Hans Joseph
1991 Advances in Computer Graphics Hardware IV  
This paper presents the architecture of a graphics engine designed to meet the above requirements. Utilizing a distributed frame buffer pixel access with a high bandwidth is achieved.  ...  Today's workstation users demand high computational performance combined with powerful graphics and a comfortable window system.  ...  On the other hand, image generation, manipulation, and rasterization comprises many different tasks and complex computations.  ... 
doi:10.1007/978-3-642-76298-7_15 fatcat:h4zvdv3befdobia3vyuot456vm

Associative Processor Architecture---a Survey

S. S. Yau, H. S. Fung
1977 ACM Computing Surveys  
The fully parallel associative processors are divided into two classes, word-orgamzed and distributed logic associative processors.  ...  A survey of the architecture of various associative processors is presented with emphasis on their characteristics, categorization, and implementation, and especially on recent developments.  ...  ACKNOWLEDGMENT The authors would like to thank Professors T. Y.  ... 
doi:10.1145/356683.356685 fatcat:zp5acsurkvhhlmdnv6keycjzyu

ParFORM: Recent development

M. Tentyukov, J.A.M. Vermaseren, H.M. Staudenmaier
2006 Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment  
We report on the status of our project of parallelization of the symbolic manipulation program FORM. We have now parallel versions of FORM running on Cluster- or SMP-architectures.  ...  Slaves manipulate these data in their local memory, and the (pre-sorted) results are collected by the master.  ...  As before, the master splits data into chunks and distributes them among slaves placing data to shared memory buffers.  ... 
doi:10.1016/j.nima.2005.11.142 fatcat:wicctnd245hqjn4p7pwybepvne

Research on Fault-Tolerant Control System for Space Modular Manipulator System

Ping YE, Han-xu SUN, Qing-xuan JIA, Xin-sheng WANG
2006 Chinese Journal of Aeronautics  
Design technologies for traditional industrial manipulator systems cannot be directly used to the space ones due to the special space environment and compactness.  ...  Considering the extremely tight constraints on mass, power consumption, volume, cost and "design-to-orbit" schedules, the fault-tolerant control system is developed mainly based on commercial-off-the-shaft  ...  It is an ARM7DTMI-based data handling computer system with Error Detection and Correction (EDAC) protected program and data memory, including two dual-redundant CAN bus interfaces.  ... 
doi:10.1016/s1000-9361(11)60354-3 fatcat:jzttzpmwofbklm3mqmux3eimpq

The Versatile Image Processor V. I. P. (Hardware Design)

G. Gugliotta, Alberto Machì
1992 IAPR International Workshop on Machine Vision Applications  
The processors operate concurrently on cluster and system shared memories through the parallel busses and exchange messages among crates and with a host system through the serial network.  ...  Modularity and alternative path availability allow to tailor the system to the problem; video bus high bandwidth and computational modules processing power allow very low processing time; usage of general  ...  Granuzzo, Project Managers of TECNINT for the continuous and Fruitful support of ideas and technical solutions to the development of VIP prototype.  ... 
dblp:conf/mva/GugliottaM92 fatcat:nkorxadqz5cmtlertw4borg2zi

Cost effectiveness of an adaptable computing cluster

Keith D. Underwood, Ron R. Sass, Walter B. Ligon
2001 Proceedings of the 2001 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '01  
With a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies found in their more expensive supercomputer  ...  This paper presents the cost implications of an architectural extension that adds reconfigurable computing to the network interface of Beowulf clusters.  ...  Hindering the technology further is its reliance on the PCI bus to transfer data to and from host memory.  ... 
doi:10.1145/582034.582088 dblp:conf/sc/UnderwoodSL01 fatcat:pn5lgbkakrhlplldvkrzswtn7y

High-performance I/O and Networking Software in Sequoia 2000

Joseph Pasquale, Eric W. Anderson, Kevin R. Fall, Jonathan S. Kay
1995 Digital technical journal of Digital Equipment Corporation  
In addition, Sequoia distributed applications require the efficient movement of very large objects, from tens to hundreds of megabytes in size.  ...  These techniques reduce or eliminate costly memory accesses, avoid unnecessary processing, and bypass system overheads to improve throughput and reduce latency.  ...  We thank Fred Templin for the technical expertise he provided us on Digital networking equipment. We thank Mike Stonebraker and Jeff Dozier for their leadership of the Sequoia 2000 project.  ... 
dblp:journals/dtj/PasqualeAFK95 fatcat:cw6rc3ukkvbnjm2zx7alzpbf2q

Page 41 of Computer Performance Vol. 4, Issue 1 [page]

1983 Computer Performance  
Even if they fulfil the speed requirements for registers and memory bus, they cannot be applied because of a pro- gressing integration of the hardware.  ...  Operand length distribution for packed (decimal) data knowledge is required about the data types and their length distribution. Four data groups have been defined (see Table 4).  ... 

Large-Scale Fast Fourier Transform [chapter]

Yifeng Chen, Xiang Cui, Hong Mei
2011 GPU Computing Gems Emerald Edition  
Bandwidth-intensive tasks such as large-scale fast Fourier transfers (FFTs) without data locality are hard to accelerate on GPU clusters because the bottleneck often lies with the PCI bus or the communication  ...  The technique of manipulating array dimensions during data transfer is the main technical contribution.  ...  Memory Hierarchy of GPU Clusters 631 Several factors have contributed to the surprising performance of our FFT on PKU McClus: first, data processing by GPUs via PCI bus is faster than sustained large memory  ... 
doi:10.1016/b978-0-12-384988-5.00039-5 fatcat:pvtrjwj33ne3pc6abkzbs5eriu

A multi-microprocessor computer system architecture

Bruce W. Arden, Alan D. Berenbaum
1975 Proceedings of the fifth symposium on Operating systems principles - SOSP '75  
A computer system design incorporating these ideas is proposed, along with its impact on memory management and process control aspects of the system's operating system.  ...  The development of microprocessors has suggested the design of distributed processing and multiprocessing computer architectures.  ...  If the high order bits matched the address of the memory module, the switch would connect the input bus with memory module bus and the data transfer could proceed.  ... 
doi:10.1145/800213.806529 dblp:conf/sosp/ArdenB75 fatcat:dnjsdq52f5bnbpw76teplmo3ru

BSPlib: The BSP programming library

Jonathan M.D. Hill, Bill McColl, Dan C. Stefanescu, Mark W. Goudreau, Kevin Lang, Satish B. Rao, Torsten Suel, Thanasis Tsantilas, Rob H. Bisseling
1998 Parallel Computing  
The role of BSPlib is to provide the infrastructure required for the user to take care of the data distribution, and any implied communication necessary to manipulate parts of the data structure that are  ...  Currently, implementations of BSPlib exist for a variety of modern architectures, including massively parallel computers with distributed memory, shared memory multiprocessors, and networks of workstations  ...  Acknowledgement The work of Jonathan Hill  ... 
doi:10.1016/s0167-8191(98)00093-3 fatcat:5dxqyd7kivhaxkzxe6qi2iwzii

A distributed I/O low-level controller for highly-dexterous snake robots

Paul Thienphrapa, Peter Kazanzides
2008 2008 IEEE Biomedical Circuits and Systems Conference  
distribute I/O and centralize processing.  ...  For robots with high locomotive sophistication, commonly seen in medical robotics, the requisite cabling and control processing can become unwieldy.  ...  (Coeur d'Alene, Idaho) and Fran Wu for their extensive help with the design and layout of the controller boards, and Mitch Williams for his help with software setup.  ... 
doi:10.1109/biocas.2008.4696861 fatcat:yhm6sapcz5gyvgeovflcxzkmki

On Tightly Coupling Models with Visualizations: The Package for Analysis and Visualization of Environmental Data

Steve R. Thorpe, Hassan A. Karimi
1997 Cartography and Geographic Information Systems  
Design goals included (1) baseline graphics with the option to export data to high-end commercial packages, (2) access and manipulation of datasets located on remote machines, (3) support for multiple  ...  We have developed the Package for Analysis and Visualization of Environmental data (PAVE), a flexible and distributed application to visualize multivariate gridded environmental datasets.  ...  The authors gratefully acknowledge the advice and assistance of the following individuals: Kiran Alapaty, Ed Bilicki,  ... 
doi:10.1559/152304097782439277 fatcat:oir4eci4nvdsjovhs37g3s2y5a

Direct GPU/FPGA Communication via PCI Express

Ray Bittner, Erik Ruf
2012 2012 41st International Conference on Parallel Processing Workshops  
Parallel processing has hit mainstream computing in the form of CPUs, GPUs and FPGAs.  ...  This is due in part to the cumbersome nature of communication between the two.  ...  This requires the FPGA to map its memory (on chip or otherwise) onto the PCIe bus so that the GPU may read or write it directly as needed.  ... 
doi:10.1109/icppw.2012.20 dblp:conf/icppw/BittnerR12 fatcat:ho6fewwoandmvh7zslhw5tcenm

Introduction to Multiprocessor I/O Architecture [chapter]

David Kotz
1996 The Kluwer International Series in Engineering and Computer Science  
W e concentrate on a study of the architectural design issues, and the e ects of di erent design alternatives. 2 Chapter 1 well as for manipulating datasets too large to t in primary memory.  ...  T h us, it is imperative that a parallel I/O architecture is provided to support the parallel computational architecture.  ...  Acknowledgements Many thanks to Nils Nieuwejaar and Jonathan Howell for their comments on early drafts of this paper, to Mike del Rosario for help understanding nCUBE details, and to Mike Best for help  ... 
doi:10.1007/978-1-4613-1401-1_4 fatcat:zdvyvbg7xrdr3jzuhis5a6vrjy
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