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Shifting register windows

G. Russell, P. Shaw
1993 IEEE Micro  
In addition, shifting register windows, a scheme based on fast hardware stack and regis--memory dribbling, has a very short register bus length.  ...  Using fewer register elements than a seven-window Sparc organjzation, shifting register windows more than bakes spiwrefd memory trafac, and reduces visible spiwrefill cycles by an order of magnitude.  ...  In Figure 3 , registers A[(n-2),(nl)] have been saved. On deallocation, register contents residing in memory should be returned to the register file.  ... 
doi:10.1109/40.229712 fatcat:qx3z255ahnfddbxngy3jbbfnzu

Design And Development Of A Soft Reconfigurable Power Electronic Control Processor

KEVIN S, D.S. DIVYA, A. AJEESH
2018 Zenodo  
This paper proposes to build a soft,platform independent,reconfigurable power electronic control processor in HDL.  ...  This can be reduced with the use of a reconfigurable control processor design in HDL and implemented on FPGA.  ...  "B00001" is used for left shift operation of data stored in R1 register and "B10002" is used for right shift operation of data stored in R2 register.  ... 
doi:10.5281/zenodo.1445483 fatcat:xublpgcfazbl5k53ncwedq6vqq

Parallel Processor Architecture with a New Algorithm for Simultaneous Processing of MIPS-Based Series Instructions

Ali Hadizadeh, Ehsan Tanghatari
2018 Emerging Science Journal  
In this architecture, new ideas for the issuance of instructions in parallel, intelligent detection of conditional jumps and memory management are presented.  ...  One of the most important processor families used in various devises is the MIPS processors. This processor family had been considered in the telecom and control industry as a reasonable choice.  ...  Managing the constraint of register file write port and executive lanes: Load instruction from memory require a write port in register file after four clocks.  ... 
doi:10.28991/ijse-01126 fatcat:3engusf3sncw3acfw4rkzmaqnm

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs

Shinya TAKAMAEDA-YAMAZAKI, Hiroshi NAKATSUKA, Yuichiro TANAKA, Kenji KISE
2015 IEICE transactions on information and systems  
For such purposes, efficiency in resource utilization is as important as high performance. This paper proposes Ultrasmall, a new soft processor architecture for FPGAs.  ...  In addition to these deviceindependent optimizations, we applied several device-dependent optimizations for Xilinx Spartan-3E FPGAs using 4-input lookup tables (LUTs).  ...  Datapath from Register File to Shift Register The memory components in Ultrasmall, such as instruction memory, data memory, and register file, use block RAMs.  ... 
doi:10.1587/transinf.2015pap0022 fatcat:txt2qfe4nbdavfnrci6oirl6w4

Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays

Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck
2010 2010 International Conference on Field Programmable Logic and Applications  
Unlike sequential processors that rely heavily on centralized storage, e.g. register files and embedded memories, spatial processors require many small storage structures to efficiently manage values that  ...  We take advantage of this distribution to optimize register storage structures for managing short-, medium-, and long-lived values.  ...  On each phase of execution the shift register is divided into two contiguous regions, the fore region that shifts data and the aft region that holds its current data.  ... 
doi:10.1109/fpl.2010.81 dblp:conf/fpl/EssenPWEH10 fatcat:n6mvwugu4neg3pi5rarczptwwm

The microarchitecture of a capability-based computer

D. A. Abramson, J. Rosenberg
1986 ACM SIGMICRO Newsletter  
The system has been specifically designed to support a very large uniform virtual memory, capability-based addressing and information hiding software modules with procedural interfaces.  ...  copies data from the inaccessable register to one in the shift chain.  ...  The high speed memory (X RAM and Y RAM) is configured as a dual ported register file. When data is written to the file, it is written to the same address in both the X RAM and the Y RAM.  ... 
doi:10.1145/19530.19546 fatcat:7xutiwut3za3xj44kquvtplnii

The microarchitecture of a capability-based computer

D. A. Abramson, J. Rosenberg
1986 Proceedings of the 19th annual workshop on Microprogramming - MICRO 19  
The system has been specifically designed to support a very large uniform virtual memory, capability-based addressing and information hiding software modules with procedural interfaces.  ...  copies data from the inaccessable register to one in the shift chain.  ...  The high speed memory (X RAM and Y RAM) is configured as a dual ported register file. When data is written to the file, it is written to the same address in both the X RAM and the Y RAM.  ... 
doi:10.1145/19551.19546 dblp:conf/micro/AbramsonR86 fatcat:nfsq6lxhmbeq5pvwtaz7ngwpgu

Book Review: Data Base Systems - A Practical Reference, by Ian Palmer

1978 IEEE Data Engineering Bulletin  
Githens, "Bulk processing in distributed logic memory," IEEE Trans. on Electron.  ...  Associative Memory System Organization References in this subsection are classified into four major categories: fully parallel systems, bit-serial systems, word-serial systems and block-oriented systems  ...  ., "Data file management in shift register memories," Internat'l . Conf., pp. 171-176, 1973. B. The photo-ready copy should be sent flat to the Editor of DBE: Dr.  ... 
dblp:journals/debu/X78a fatcat:2qr2zq7vbnfbpk7zl24ezyexqe

Elliptic-Curve-Based Security Processor for RFID

Yong Ki Lee, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede
2008 IEEE transactions on computers  
As we work with large numbers, the register file is the most critical component in the architecture.  ...  By combining several techniques, we are able to reduce the number of registers from nine to six in the EC processor.  ...  Although the register file in Fig. 4 is a circular shift register file, each register is independently controlled for efficient management.  ... 
doi:10.1109/tc.2008.148 fatcat:drkz7jgrdfccdk6bd7utpauh5i

The IBM RT PC ROMP processor and memory management unit architecture

R. O. Simpson, P. D. Hester
1987 IBM Systems Journal  
In this paper we first give some details of the implementation of the ROMP processor and its Memory Management Unit (MMU).  ...  The ROMP processor is the microprocessor used in the ISM RT PC. It is a 32-bit processor with an associated memory management unit implemented on two chips.  ...  The paired shifts provide nondestructive shifts that shift a specified GPR a given amount, and place the result in a different register (the other register of a register pair) without altering the source  ... 
doi:10.1147/sj.264.0346 fatcat:wrgsqd4e2ffzlhhpaxdufunbb4

Dynamic context management for low power coarse-grained reconfigurable architecture

Yoonjin Kim, Rabi N. Mahapatra
2009 Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09  
In this paper, we propose a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA.  ...  Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array.  ...  data with register file (REG_FILE).  ... 
doi:10.1145/1531542.1531555 dblp:conf/glvlsi/KimM09 fatcat:i47b5d2tgfhj3npmwp6m4vuajq

From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware

Haibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-chung Yew, Frederic T. Chong
2008 2008 International Symposium on Computer Architecture  
SHIFT leverages existing architectural support for speculative execution to track tainted state in registers and needs to instrument only load and store instructions to track tainted state in memory using  ...  A security assessment shows that SHIFT can detect both low-level memory corruption exploits as well as high-level semantic attacks with no false positives.  ...  ., exception tokens) in registers and SHIFT uses a bitmap to maintain the tags in memory.  ... 
doi:10.1109/isca.2008.18 dblp:conf/isca/ChenWYZYC08 fatcat:yjpye3xdfncgljndzhmu3jm6n4

From Speculation to Security

Haibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-chung Yew, Frederic T. Chong
2008 SIGARCH Computer Architecture News  
SHIFT leverages existing architectural support for speculative execution to track tainted state in registers and needs to instrument only load and store instructions to track tainted state in memory using  ...  A security assessment shows that SHIFT can detect both low-level memory corruption exploits as well as high-level semantic attacks with no false positives.  ...  ., exception tokens) in registers and SHIFT uses a bitmap to maintain the tags in memory.  ... 
doi:10.1145/1394608.1382156 fatcat:4rfuygu6vjgh5jmb5k7dt5ubmu

Embedded linux implementation on a commercial digital TV system

Sang-Pil Moon, Joo-Won Kim, Kuk-Ho Bae, Jae-Cheon Lee, Dae-Wha Seo
2003 IEEE transactions on consumer electronics  
Especially in the case of bidirectional broadcasting, it should manage the return channel created by the Internet, PSTN, and so on.  ...  In this paper, we modified the embedded Linux kernel and the cross development environment for a big-endian system, redesigned device drivers for kernel execution, and configured system memory map in order  ...  to the SDL (serial data line) by the shift register.  ... 
doi:10.1109/tce.2003.1261247 fatcat:imx3q7uaafbtta3xymcemrdnce

Risc Processor Design In Vlsi Technology Using The Pipeline Technique

Rakesh M.R
2015 Zenodo  
Harvard Architecture is used which has distinct program memory space and data memory space. The only load and store is used to communicate with data memory.  ...  Load instruction which load the data value from memory to register and store instruction which store the value from register to RAM memory.  ...  Store result (ST): Register-Register ALU instruction or Load instruction: Write the result into the register file, whether it comes from the memory system (for a load) or from the ALU (for an ALU instruction  ... 
doi:10.5281/zenodo.32438 fatcat:fnrvtvenznh6fdf6hrcugemsru
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