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Data Criticality in Network-On-Chip Design

Joshua San Miguel, Natalie Enright Jerger
2015 Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15  
(iz)) ... = cell->v[j].z; } Defining Criticality x y z x y z x y z x y z x y z cell->v Data Liveness 39 Data liveness measures the degree of spatial locality in an application  ...  -on-arrival (live): used at least once during its cache lifetime. Dead-on-arrival (dead): never used during its cache lifetime.  ...  Addressing Criticality 61 A criticality-aware NoC design needs to: 1. Predict the criticality of a word prior to fetching it. 2. Separate the fetching of words based on their criticality. 3.  ... 
doi:10.1145/2786572.2786593 dblp:conf/nocs/MiguelJ15 fatcat:45yvdkfcyzfsvlqezjgaclvqby

Transaction-Aware Network-on-Chip Resource Reservation

Zheng Li, Changyun Zhu, Li Shang, R. Dick, Yihe Sun
2008 IEEE computer architecture letters  
In this work, we address the latency issue of on-chip network design and propose dynamic in-network resource reservation techniques that are guided by highlevel data transaction information.  ...  Experiments with multithreaded benchmarks demonstrate that the proposed techniques reduce on-chip data access latency and demonstrate the importance of considering transaction-level information in network  ...  As described in the previous section, on-chip network latency includes Trequest and T data .  ... 
doi:10.1109/l-ca.2008.9 fatcat:q2c4u7ow5jaujhrfvsdccoodzu

Latency criticality aware on-chip communication

Zheng Li, Jie Wu, Li Shang, R.P. Dick, Yihe Sun
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
This paper describes a new method to minimize onchip network latency, which is motivated by the observation that only a small percentage of on-chip data and protocol traffic is latency-critical.  ...  It offers high throughput and excellent scalability for on-chip data and protocol transactions.  ...  Our study shows that, in a tiled shared-memory CMP design in which the network is used to relay L2 cache data traffic, network latency can account for 73.3% on-chip data access latency (see Section 2)  ... 
doi:10.1109/date.2009.5090820 dblp:conf/date/LiWSDS09 fatcat:wyygsdkuire57bhuw4ecwzvwbq

On-Chip Interconnection Networks of the TRIPS Chip

P. Gratz, Changkyu Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S.W. Keckler, D. Burger
2007 IEEE Micro  
On-chip routed networks are emerging in different multicore chip designs.  ...  a shift toward networks on chip (NoCs).  ... 
doi:10.1109/mm.2007.4378782 fatcat:nripchy7qbaatdnfluqdzmrm7q

A high-performance low-power nanophotonic on-chip network

Zheng Li, Jie Wu, Li Shang, Alan R. Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun
2009 Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09  
This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network.  ...  On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and  ...  Together, the proposed design provides power-efficient support for both latency-critical and throughput-critical on-chip communication traffic of many-core systems.  ... 
doi:10.1145/1594233.1594305 dblp:conf/islped/LiWSMVFPS09 fatcat:csin272uo5gcraf6mqkcivsf3m

A systematic eight port network on chip router with reduced critical section problem

T. Saipriyadharshini, R. Parameshwaran
2014 Contemporary Engineerng Sciences  
Network on chip is an emerging technology which provides data reliability and high speed with less power consumption.  ...  The central component of NOC architecture is a router that should be designed in an efficient manner. In NoC designs, parallel transfers of data between the PEs are possible.  ...  Network on chip architecture better supports the integration of SOC which consists of on chip packet switched network.  ... 
doi:10.12988/ces.2014.4210 fatcat:it4yp2dbfrfm5nhxuk5rrtcz5a

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication [article]

Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
2020 arXiv   pre-print
Decades of research on on-chip networks enabled cache-coherent shared-memory multiprocessors.  ...  In this work, we present a modular, topology-agnostic, high-performance on-chip communication platform.  ...  Design space exploration and electronic design automation (EDA) for on-chip networks is a research field in its own right.  ... 
arXiv:2009.05334v1 fatcat:42ttl7lytzcx3npvc7gjvtabjy

Guest Editors' Introduction: Silicon Nanophotonics for Future Multicore Architectures

Sudeep Pasricha, Yi Xu
2014 IEEE design & test  
(SNR) and performance in optical on-chip networks.  ...  Her research interests include the network-on-chip designs for 2-D/3-D chips, thermal modeling, and nanophotonic network architecture.  ... 
doi:10.1109/mdat.2014.2355512 fatcat:ceocas5jknbkheaakvet2iyzeq

Efficient Instruction and Data Caching for High Performance Embedded Processors

A. Ferrerón Labari, D. Suárez Gracia, V. Viñals Yúfera
1970 Jornada de Jóvenes Investigadores del I3A  
The key points are decoupling the functionality, and utilizing three specialized networks on-chip.  ...  Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest  ...  The key points are decoupling the functionality, and utilizing three specialized networks on-chip.  ... 
doi:10.26754/jji-i3a.201201788 fatcat:7ud77yodjja75jt2vvaz5z2hfe

A high performance network-on-chip scheme using lossless data compression

Hong-Sik Kim, Youngha Jung, Hyunjin Kim, Jin-Ho Ahn, Woo-Chan Park, Sungho Kang
2010 IEICE Electronics Express  
A new NoC (network on chip) architecture using lossless data compression and decompression to improve the performance and power efficiency of the on-chip interconnect is proposed.  ...  In the proposed NoC scheme, the sender compresses the data to be transferred in order to reduce the number of data packets and the receiver decompresses the encoded data to restore the original data.  ...  Recently, in order to guarantee the performance and reliability of the on-chip interconnect, a new design methodology called as an NoC (network on chip), has been introduced [2] .  ... 
doi:10.1587/elex.7.791 fatcat:2v3unxvlqrciln675wua5x337i

Synchronous Chip-to-Chip Communication with a Multi-Chip Resonator Clock Distribution Network [article]

Jonathan Egan, Max Nielsen, Joshua Strong, Vladimir V. Talanov, Ed Rudman, Brainton Song, Quentin Herr, Anna Herr
2021 arXiv   pre-print
In such systems, performance of the data link between chips mounted on a multi-chip module (MCM) is a critical driver of performance.  ...  In this work we report a synchronous data link using Reciprocal Quantum Logic (RQL) enabled by resonant clock distribution on the chip and on the MCM carrier.  ...  and assistance with design.  ... 
arXiv:2109.00560v1 fatcat:jf3ib3a5tfhsbd2krolriv67cm

Thread criticality support in on-chip networks

Yuho Jin, Ruisheng Wang, Woojin Choi, Timothy Mark Pinkston
2010 Proceedings of the Third International Workshop on Network on Chip Architectures - NoCArc '10  
As the communication latency of threads affects thread criticality, it should be considered and optimized. In this work, we explore thread criticality support in on-chip networks.  ...  The on-chip network is an increasingly important component that services communication of threads running on cores.  ...  The research described in this paper was supported, in part, by the National Science Foundation (NSF) grants CCF-0541417, CCF-0946388, and a CIFellows Postdoc Award.  ... 
doi:10.1145/1921249.1921253 dblp:conf/micro/JinWCP10 fatcat:6pltmhte25g4va2myvlz3nnvba

NETWORK ON-CHIP AND ITS RESEARCH CHALLENGES

Paramasivam K.
2015 ICTACT Journal on Microelectronics  
Networks-On-Chip (NoCs) have been proposed as a promising solution for power, performance demands and scalability of next generation Systems-On-Chip (SOCs) to overcome the several challenges of current  ...  Future SoC design needs lot of innovations and creativity to explore its complete features. Research on NoC is mandatory at this critical juncture.  ...  This paper gives an overview of state-of-the art network-on-chip. The emerging field of NoC research and design challenges were discussed.  ... 
doi:10.21917/ijme.2015.0015 fatcat:butio7bjjjbgxdtrqnquaei2wa

Network-on-Chip: A State-of-the-art Review

Seema Seema, Pawan Kumar Dahiya
2017 IOSR Journal of VLSI and Signal processing  
In this paper a study treats an outstanding concept for system-on-chip communication introduced as communication network on-chip (NoC).  ...  As data intensive applications have emerged and processing power has increased, the threat of the communication components on single-chip systems introduced network on chip (NoC).  ...  Conclusion The advancement in SoC introduced a platform known as network-on-chip (NoC). The NoC provides on-chip communication that was getting more and more complex in SoC.  ... 
doi:10.9790/4200-0704012935 fatcat:2lvngq24prdjtevtkpqeqkv67u

A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR

Roman Obermaisser, Hubert Kraut, Christian Salloum
2008 2008 Seventh European Dependable Computing Conference  
On-chip TMR improves the reliability of a MPSoC, e.g., by tolerating a transient fault in one of three replicated IP cores.  ...  This paper introduces such an architecture, which supports the integration of multiple, heterogeneous IP cores that are interconnected by a time-triggered Network-on-a-Chip (NoC).  ...  Acknowledgments This work has been supported in part by the European IST project ARTIST2 under project No. IST-004527 and the national FITIT project TT-SoC under grant number 813299/7852.  ... 
doi:10.1109/edcc-7.2008.20 dblp:conf/edcc/ObermaisserKS08 fatcat:apeszpmzbzczfgozr2lkwmkrra
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