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The orders-of-magnitude faster testing in post-silicon enables designers to achieve much higher coverage before customer release, but only if the limitations of this technology in diagnosis and internal ... In this work, we unlock the full performance of postsilicon validation through Dacota, a new high-coverage solution for validating memory operation ordering in CMPs. ... Runtime solutions to the problem of memory subsystem correctness have emerged to ensure the correctness of multi-core designs deployed in the field. Meixner et. al. ...doi:10.1109/hpca.2009.4798278 dblp:conf/hpca/DeOrioWB09 fatcat:33h2gkvx3vf6toxhl4t2t2nh5q
Finally we present some of today's general trends in post-silicon validation research. ... Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. ... The second solution focuses on the validation of the memory subsystem in multi-core designs, specifically of the cache coherence protocol. ...doi:10.1109/aspdac.2010.5419885 dblp:conf/aspdac/Bertacco10 fatcat:ijenghr7mrcfboug5hfycuwnpm
Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. ... To accelerate post-silicon debug, BackSpace [1, 2] employs on-chip monitoring circuitry and off-chip formal analysis to provide a trace of states that lead up to a crash state. ... This work was funded by the Semiconductor Research Corporation(SRC) TaskID: 1586.001. ...doi:10.1109/isqed.2010.5450450 dblp:conf/isqed/KuanWA10 fatcat:ukqyn3strbevjbhi7ofvszxnga