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ATCA-based computation platform for data acquisition and triggering in particle physics experiments

Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch
2008 2008 International Conference on Field Programmable Logic and Applications  
The system represents a highly reconfigurable and scalable solution for multiple applications.  ...  An ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed.  ...  To release the CPU from moving data back and forth between the memory and the IP, DMA and interrupt are enabled in the IPIF.  ... 
doi:10.1109/fpl.2008.4629946 dblp:conf/fpl/LiuLYPKXJWLLLJ08 fatcat:p2mrxt3zebfi5aiw6fybyv7p4m

Optimizing Compiler for the CELL Processor

A.E. Eichenberger, K. O'Brien, K. O'Brien, Peng Wu, Tong Chen, P.H. Oden, D.A. Prener, J.C. Shepherd, Byoungro So, Z. Sura, A. Wang, Tao Zhang (+2 others)
2005 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)  
on the CELL processor.  ...  Developed for multimedia and game applications, as well as other numerically intensive workloads, the CELL processor provides support both for highly parallel codes, which have high computation and memory  ...  Also, in our case the processor cores are on the same chip, and even though the SPEs rely on DMA transfers, all cores use the same virtual memory space to address shared data.  ... 
doi:10.1109/pact.2005.33 dblp:conf/IEEEpact/EichenbergerOOWCOPSSSWZZG05 fatcat:e54xideiibbn7dp5tqsh34oxgq

Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture

A. E. Eichenberger, J. K. O'Brien, K. M. O'Brien, P. Wu, T. Chen, P. H. Oden, D. A. Prener, J. C. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang (+5 others)
2006 IBM Systems Journal  
globally coherent cache and eight synergistic processor elements (SPEs), each consisting of a processor designed for streaming workloads, a local memory, and a globally coherent DMA (direct memory access  ...  Game applications feature highly parallel code for functions such as game physics, which have high computation and memory requirements, and scalar code for functions such as game artificial intelligence  ...  While the PPE makes use of a conventional two-level cache, each SPE draws data and instructions from its own small memory, internal to the chip.  ... 
doi:10.1147/sj.451.0059 fatcat:x67guy5bpragrl3hookkbsqpn4

Video Encoder Implementation on Tilera's TILEPro64TM Multicore Processor [chapter]

Jose Parera-Bermudez, Javier Casajus-Quiros, Igor Arambasic
2013 Design and Architectures for Digital Signal Processing  
The authors also acknowledge the continuing support and cooperation of Datatech SDA for ongoing developments of Tilera's processor capabilities: real-time video analysis, virtual advertising and augmented  ...  Project TEC2009-14219-C03-01 also provided support for this work.  ...  2660 Gbps On-chip Cache Memory Bandwidth 1774 Gbps Table 1.  ... 
doi:10.5772/53429 fatcat:3jpldmgy4ja3hivdzgwqjmuz2m

The integrated low-level trigger and readout system of the CERN NA62 experiment

R. Ammendola, B. Angelucci, M. Barbanera, A. Biagioni, V. Cerny, B. Checcucci, R. Fantechi, F. Gonnella, M. Koval, M. Krivda, G. Lamanna, M. Lupi (+14 others)
2019 Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment  
The NA62 TDAQ system is rather unique in allowing full flexibility on this scale, allowing in principle any information available from the detector to be used for triggering.  ...  The requirements of a large and fast data reduction in a high-rate environment for a medium-scale, distributed ensemble of many different sub-detectors led to the concept of a fully digital integrated  ...  Data are DMA-read from GPU memory; the kernel device driver instructs the NIC by filling a "descriptor" into a dedicated DMA-accessible memory region ("TX ring").  ... 
doi:10.1016/j.nima.2019.03.012 fatcat:nekjppzjdbegrmdczmupydyile

Optimizing OpenCL Code for Performance on FPGA: k-means Case Study with Integer Data Sets

Nuno Paulino, Joao Canas Ferreira, Joao M.P. Cardoso
2020 IEEE Access  
We evaluate the use of task-kernels versus NDRange kernels, data vectorization, the use of on-chip local memories, and data transfer optimizations by exploiting burst access inference.  ...  To determine the effects of different data set characteristics, and to determine the gains from specialization based on number of attributes, we generated a total of 12 integer data sets.  ...  on-chip memory or channels.  ... 
doi:10.1109/access.2020.3017552 fatcat:uifsjk5225bxpojn2kf4r5cmeq

Understanding Screaming Channels: From a Detailed Analysis to Improved Attacks

Giovanni Camurati, Aurélien Francillon, François-Xavier Standaert
2020 Transactions on Cryptographic Hardware and Embedded Systems  
For example, we learn about the coexistence of intended and unintended data, the role of distance and other parameters on the strength of the leak, the distortion of the leakmodel, and the portability  ...  On the one side, this work lowers the bar for more realistic attacks, highlighting the importance of the novel attack vector.  ...  Acknowledgments The authors acknowledge the support of SeCiF project within the French-German Academy for the Industry of the future as well as the support by the DAPCODS/IOTics ANR 2016 project (ANR-16  ... 
doi:10.13154/tches.v2020.i3.358-401 dblp:journals/tches/CamuratiFS20 fatcat:qadpmmfnbzhihmycq7vamkjuce

The MEG detector for μ +→e+ γ decay search

J. Adam, X. Bai, A. M. Baldini, E. Baracchini, C. Bemporad, G. Boca, P. W. Cattaneo, G. Cavoto, F. Cei, C. Cerri, M. Corbo, N. Curalli (+68 others)
2013 European Physical Journal C: Particles and Fields  
The MEG (Mu to Electron Gamma) experiment has been running at the Paul Scherrer Institut (PSI), Switzerland since 2008 to search for the decay by using one of the most intense continuous μ^+ beams in the  ...  The trigger system, the read-out electronics and the data acquisition system are also presented in detail.  ...  David Stoker of the University of California, Irvine, for his careful proofreading of the manuscript and its improvements.  ... 
doi:10.1140/epjc/s10052-013-2365-2 fatcat:ygo3rdnkrjd5hb4c2khlv6o5hq

Motion Systems [chapter]

2009 Principles of Flight Simulation  
Similarly at the receiver, the data is copied from the databus as serial data to memory using DMA.  ...  The network interface is programmed to copy this data from memory to the databus, using direct memory access (DMA) independent of the processor.  ...  in terms of subjective assessment, particularly for braking and steering on the ground; • Eventually, a motion trial requires the subjective analysis of pilots, with potential variability in the assessment  ... 
doi:10.1002/9780470685662.ch10 fatcat:4w57z4rbojbavjc42xzsj45o4q

A Reconfigurable Multipurpose SoC Mobile Platform for metal detection

Omran Al Rshid Abazeed, Naram Mhaisen, Youssef Al-Hariri, Naveed Nawaz, Abbes Amira
2018 Qatar Foundation Annual Research Conference Proceedings Volume 2018 Issue 3   unpublished
access (DMA) controller, FPGA configuration manager, and clock and reset managers • On-chip RAM and boot ROM continued... (1) Contact Intel for availability.  ...  For modules without an integrated DMA controller, an additional DMA controller module provides up to eight channels of high-bandwidth data transfers.  ... 
doi:10.5339/qfarc.2018.ictpd1076 fatcat:gz27u2na6nay5h5372ftecs6e4

A high data rate readout system for particle detectors based on FPGA-to-server ethernet connections and the eXpress Data Path technology

Carsten Dülsen, Bergische Universität Wuppertal
The increased resolution and the increased number of front-end (FE) chips also leads to a drastically increased data rate, which is necessary to transfer all event information from the detector in a timely  ...  Therefore, an interface between the hardware systems and the software running on a remote server needs to be implemented.  ...  Timo Göhring, for performing the investigations on a broader parameter set. I thank them all for their hard work.  ... 
doi:10.25926/7a9g-rq40 fatcat:z7tu5eds45fznbza7o2hiwy5ci

Radio interferometry techniques for geodesy

1979 Bulletin Géodésique  
We would like to thank Irwin Shapiro for enlightening discussions regarding the VLBI data analysis.  ...  Correlation and further processing of the data is carried out, for the most part, using the threestation Mark II processor at the Max Planck Institut fiir Radioastronomie in Bonn, Germany.  ...  Also, the design will directly accommodate 64-kbit memory chips when they become economical, expanding the memory capacity to 4 Megabits.  ... 
doi:10.1007/bf02521643 fatcat:2wf6omvyrfeb7iq56xseifrpxe

Hardware Architecture of an XML/XPath Broker/Router for Content-Based Publish/Subscribe Data Dissemination Systems

Fadi El-Hassan, Université D'Ottawa / University Of Ottawa, Université D'Ottawa / University Of Ottawa
Furthermore, such a system-on-chip architecture is upgradable, if any future hardware add-ons are needed. However, the current arc [...]  ...  Moreover, the broker employs effective mechanisms for content-based routing, so as subscriptions, publications, and notifications are routed through the network based on content.  ...  In one more clock cycle, the data is realigned and placed on either the U-String or the V-String bus.  ... 
doi:10.20381/ruor-3564 fatcat:dsr2nie3hvhbbprgayiqn4si4u

A Modified SMO Algorithm for SVM Regression and Its Application in Quality Prediction of HP-LDPE [chapter]

Hengping Zhao, Jinshou Yu
2005 Lecture Notes in Computer Science  
-Demonstrations of Methods Applicability DMA -U.S.  ...  Diaster Response Group CDRL -Contract Data Requirements List CD-ROM -Compact Disk -Read Only Memory CDS -Compliance Data System CDS/ISIS -CDS/Integrated Set of Information System CE -Calibration  ... 
doi:10.1007/11539087_79 fatcat:ydvvlhkkh5grhh7r6rv66y2tia

A metadata-enhanced framework for high performance visual effects

Jay L. T. Cornwall, Paul Kelly, EPSRC
for optimal aligned memory access.  ...  the optimised source to the vendor compiler for lower-level optimisation.  ...  memory, realigning staging CUDA function.  ... 
doi:10.25560/5854 fatcat:bxqpckuu3zhjllry2eb7vneawq
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