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DCC: A Dependable Cache Coherence Multicore Architecture

Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas
2011 IEEE computer architecture letters  
In this paper, we propose a dependable cache coherence architecture (DCC) that combines the traditional directory protocol with a novel executionmigration-based architecture to ensure dependability that  ...  Cache coherence lies at the core of functionally-correct operation of shared memory multicores.  ...  On the other hand, a shared-L1/L2 configuration unifies the physically distributed per-core caches into a logically shared cache.  ... 
doi:10.1109/l-ca.2011.3 fatcat:6ix5nvsl6jggdkkki3ywdn22k4


Đồng Mạnh Cường, Trần Minh Châu
2021 Tạp chí Khoa học và Công nghệ - Đại học Thái Nguyên  
Chúng tôi cải thiện quy trình ước lượng của mô hình này bằng cách sử dụng phương pháp ước lượng Bayes.  ...  Cách tiếp cận này giúp xác định sự biến động của mối tương quan giữa các tài sản trong các chu kỳ thị trường chứng khoán khác nhau.  ...  We observed that the correlations between VN-index and other stock markets were consistently positive regardless of the state of the world economy.  ... 
doi:10.34238/tnu-jst.4365 fatcat:s4fytexzjrfgjoum5peodg2c6y

Distributed cloud computing in high energy physics

Randall Sobie
2014 Proceedings of the 2014 ACM SIGCOMM workshop on Distributed cloud computing - DCC '14  
In particular, we highlight our use of a distributed cloud computing system that integrates both private and public IaaS clouds into a unified infrastructure.  ...  We describe our experience using the distributed cloud and our plans to make the system context-aware in order to scale to larger workloads and run data-intensive HEP applications.  ...  The recorded data consists of large numbers of single events.  ... 
doi:10.1145/2627566.2627578 dblp:conf/sigcomm/Sobie14 fatcat:zpzlyyhkhrh45affc5moz2oxqe

Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces

Milena Milenkovic, Aleksandar Milenkovic, Martin Burtscher
2007 2007 Data Compression Conference (DCC'07)  
Hence, trace files tend to be very large and difficult to use and distribute.  ...  Compression of more complex trace records can exploit trace locality by storing relevant values in a cache-like structure so that a compressed trace consists of cache hit and miss information [18] .  ... 
doi:10.1109/dcc.2007.10 dblp:conf/dcc/MilenkovicMB07 fatcat:ynbflo53ffdctezkx5you7s4xe

Coverage of a microarchitecture-level fault check regimen in a superscalar processor

Vimal Reddy, Eric Rotenberg
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
They should be consistent. If not, there is a fault in either the BTB logic or the decode logic.  ...  However, RNA1 cannot detect faults in which an erroneous mapping appears consistent among all the structures.  ... 
doi:10.1109/dsn.2008.4630065 dblp:conf/dsn/ReddyR08 fatcat:unq3sfknhjbgrnmpcbkjeqjh3y

Detouring: Translating software to circumvent hard faults in simple cores

Albert Meixner, Daniel J. Sorin
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
Our initial implementation of Detouring tolerates hard faults in several hardware components, including the instruction cache, registers, functional units, and the operand bypass network.  ...  The OR1200 consists of roughly 25000 gates, excluding the register file.  ...  For this analysis we assumed faults to be uniformly distributed.  ... 
doi:10.1109/dsn.2008.4630073 dblp:conf/dsn/MeixnerS08 fatcat:4ye3u5fb75arhmdgixuj6v3jdm

A fault-tolerant directory-based cache coherence protocol for CMP architectures

Ricardo Fernandez-Pascual, Jose M. Garcia, Manuel E. Acacio, Jose Duato
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
We propose to deal with this kind of failures at the level of the cache coherence protocol instead of ensuring the reliability of the network itself.  ...  Particularly, we have extended a directorybased cache coherence protocol to ensure correct program semantics even in presence of transient failures in the interconnection network.  ...  The L2 cache is logically shared by all cores but it is physically distributed among all tiles. Each tile has its network interface to connect to the on-chip interconnection network.  ... 
doi:10.1109/dsn.2008.4630095 dblp:conf/dsn/PascualGAD08 fatcat:6wg62nrhy5bxzh54vmplcaadye

Marlin: A High Throughput Variable-to-Fixed Codec Using Plurally Parsable Dictionaries

Manuel Martinez, Monica Haurilet, Rainer Stiefelhagen, Joan Serra-Sagrista
2017 2017 Data Compression Conference (DCC)  
The code emitted consists of the indexes that point to such words.  ...  For efficiency reasons, the dictionary set must be small, as switching dictionaries trashes the cache. We employ 11 dictionaries per distribution. Alphabet size.  ... 
doi:10.1109/dcc.2017.74 dblp:conf/dcc/MartinezHSS17 fatcat:dpy6dpgc6rbpbcqhqsyh4tyqcu

Tempest: Soft state replication in the service tier

Tudor Marian, Mahesh Balakrishnan, Ken Birman, Robbert van Renesse
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
Most often than not, these middleware solutions handle soft state using distributed cache infrastructures, at times relying on third party products like Oracle Coherence [29] or GemFire Enterprise [  ...  Client requests were drawn from a Zipf distribution (with s=1) over the space of object identifiers -reads and writes equally distributed.  ... 
doi:10.1109/dsn.2008.4630091 dblp:conf/dsn/MarianBBR08 fatcat:o6bq7lxtsvbpnansxkiosmk6me

Experiences with formal specification of fault-tolerant file systems

Roxana Geambasu, Andrew Birrell, John MacCormick
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
We wrote formal specifications for three real-world fault-tolerant file systems and used them to: (1) expose design similarities and differences; (2) clarify and mechanically verify consistency properties  ...  The advantages of formal specifications have been previously reported for various types of systems, e.g.: caches [11] , space shuttle software [6] , and local and distributed file systems [18, 20] .  ...  and distributed file systems [18, 20, 21] , and many others (a wealth of examples are presented in a survey [5] ).  ... 
doi:10.1109/dsn.2008.4630075 dblp:conf/dsn/GeambasuBM08 fatcat:vfy6zr52mrgu7gxe75dsj7wf5m

Scheduling algorithms for unpredictably heterogeneous CMP architectures

Jonathan A. Winter, David H. Albonesi
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
, 1 cycle latency Data TLB 32 entry, fully assoc., 2 ports L2 Cache 1MB, 8-way assoc., 1 port, 10 cycle latency Main memory 1 port, 200 cycle latency Our baseline architecture consists of an  ...  Distributed built-in self-testing and checkpointing techniques are devised by Shyam et al. [30] for detecting and recovering from defects. Finally, Aggarwal et al.  ... 
doi:10.1109/dsn.2008.4630069 dblp:conf/dsn/WinterA08 fatcat:eogaq24nyvck5ppg7xp2ojejge

Enhanced server fault-tolerance for improved user experience

Manish Marwah, Shivakant Mishra, Christof Fetzer
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
Stateless load balancers distribute incoming client packets among the proxies.  ...  Again, we assume that the images are already cached and do not issues those requests in our experiments.  ... 
doi:10.1109/dsn.2008.4630085 dblp:conf/dsn/MarwahMF08 fatcat:rhyfzy6b65g27mercklhtifure

A Space Efficient Direct Access Data Structure

Gilad Baruch, Shmuel T. Klein, Dana Shapira
2016 2016 Data Compression Conference (DCC)  
For any distribution, there are many different Huffman trees, and for some distributions, there might even exist Huffman trees of different depths.  ...  The experiments were conducted on a machine running 64 bit Linux Ubuntu with an Intel Core i7-4720 at 2.60GHz processor, 6144K L3 cache size of the CPU, and 4GB of main memory.  ... 
doi:10.1109/dcc.2016.61 dblp:conf/dcc/BaruchKS16 fatcat:37u65toapjbqnnj6iu3253xs6e

Reliability of flat XOR-based erasure codes on heterogeneous devices

Kevin M. Greenan, Ethan L. Miller, Jay J. Wylie
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
Traditionally, this is done to improve performance: to reduce response time of accesses, to balance load, and for distributed caching.  ...  Uniform configurations consist of one 100k device and one 500k device; the remaining devices have MTTF values uniformly distributed between η = 100000 and η = 500000.  ... 
doi:10.1109/dsn.2008.4630083 dblp:conf/dsn/GreenanMW08 fatcat:r6ul3pkndbh75oh7u4yek2z3gy

Probabilistic quorum systems in wireless ad hoc networks

Roy Friedman, Gabriel Kliot, Chen Avin
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
Quorums are a basic construct in solving many fundamental distributed computing problems.  ...  The intersection property enables maintaining consistency of actions taken by nodes of a distributed system.  ...  Caching. Caching of advertisement requests or lookup replies that pass through nodes can significantly reduce the lookup overhead.  ... 
doi:10.1109/dsn.2008.4630096 dblp:conf/dsn/FriedmanKA08 fatcat:j4qk5vkfijeb7bc5yhnntbgttu
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