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Dynamic adaptive streaming over CCN: A caching and overhead analysis

Yaning Liu, Joost Geurts, Jean-Charles Point, Stefan Lederer, Benjamin Rainer, Christopher Muller, Christian Timmerer, Hermann Hellwagner
2013 2013 IEEE International Conference on Communications (ICC)  
Due to segment caching within the network, subsequent requests for the same content can be served quicker.  ...  We present two sets of experiments to evaluate the performance of DASC showing that throughput indeed improves.  ...  of cached segments on CCN nodes in Table I with the first column identifying the sequence number of DASC clients and the first row showing the playback rates of cached segments on the CCN node.  ... 
doi:10.1109/icc.2013.6655116 dblp:conf/icc/LiuGPLRMTH13 fatcat:2wzfnknbeff47jw7bpncvriy5a

DASC-DIR: a low-overhead coherence directory for many-core processors

Alberto Ros, Manuel E. Acacio
2014 Journal of Supercomputing  
Cache coherence in this context is guaranteed by means of a directory-based protocol.  ...  With this memory model, all on-chip storage is used for private and shared caches that are kept coherent by hardware.  ...  DASC-3bits_RR 11. DASC-3bits_FT 12. DASC-3bits_DARR 13. DASC-2bits_RR 14. DASC-2bits_FT 15.  ... 
doi:10.1007/s11227-014-1325-4 fatcat:ae3zlcyoxvfpbcna4oklxon6im

Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces

Milena Milenkovic, Aleksandar Milenkovic, Martin Burtscher
2007 2007 Data Compression Conference (DCC'07)  
The data address trace compression utilizes a data address stride cache (DASC).  ...  The first level of the trace compressor encompasses an instruction stream cache (SC) and a data address stride cache (DASC).  ... 
doi:10.1109/dcc.2007.10 dblp:conf/dcc/MilenkovicMB07 fatcat:ynbflo53ffdctezkx5you7s4xe

MPSoC hypervisor: The safe & secure future of avionics

Steven H. VanderLeest, DornerWorks Dagan White
2015 2015 IEEE/AIAA 34th Digital Avionics Systems Conference (DASC)  
tasks real-time tasks, lockstep capable D EGG on data cache and tightly-coupled memory, parity on instruction cache D 1.7 DMIPS/MHz per core, single/lock 1 K DMIPS, dual core 2K DMIPS �Yirr O � E R \R9  ...  and L 1 data cache, parity on L 1 instruction cache D Each core can be enabled or disabled independently D Dual-core Cortex-R5 Real-time Processor Unit (RPU) D up to 600MHz D Isolation of critical/precise  ... 
doi:10.1109/dasc.2015.7311612 fatcat:khwkyf73pbf6hixufvpkrleohy

Towards a cloud consumers credibility assessment and trust management of cloud services

E. Priyadharshini, V. Vijayakumar, M.D. Abdul Quadir
2018 EAI Endorsed Transactions on Cloud Systems  
The DaSCE utilizes the threshold DaSCE and also evaluating its performance based on time consuming and also formal model to analyse the working of DaCSE using high level petrinets.  ...  Figure 2 . 2 Trust Management Service Caching: T (CSC) starts caching trust results (CSC) and T (CSP) start caching trust results (CSP) 5.  ... 
doi:10.4108/eai.16-5-2018.154775 fatcat:y65te6igcrbhpfxbgo2s7t3dgy

Distributed approximate spectral clustering for large-scale datasets

Mohamed Hefeeda, Fei Gao, Wael Abd-Almageed
2012 Proceedings of the 21st international symposium on High-Performance Parallel and Distributed Computing - HPDC '12  
Our local cluster is composed of five machines, each is equipped with Intel Core2 Duo Processor E6550 (4M Cache, 2.33 GHz, 1333 MHz FSB) and 1 GB DRAM.  ...  Intermediate results of hashing (buckets) are stored on S3 and then incrementally processed by DASC to produce final results. Thus, DASC can handle huge datasets.  ... 
doi:10.1145/2287076.2287111 dblp:conf/hpdc/HefeedaGA12 fatcat:qgpd4gnvmfbubcnn6waw73mfoi

Table of contents

2019 2019 IEEE 35th International Conference on Data Engineering Workshops (ICDEW)  
Vienna University of Technology, Industrial Software (INSO)), and Thomas Grechenig (Vienna University of Technology, Industrial Software (INSO)) International Workshop on Data -Driven Smart Cities (DASC  ...  Recipes (DECOR) Computational Models for the Evolution of World Cuisines 85 Rudraksh Tuwani (Indraprastha Institute of Information Technology ( Cost/Performance in Modern Data Stores: How Data Caching  ... 
doi:10.1109/icdew.2019.00004 fatcat:f2qwa6cndnejjkorlwhiiyh34a

A fully associative software-managed cache design

Erik G. Hallnor, Steven K. Reinhardt
2000 SIGARCH Computer Architecture News  
a conventional cache as these CPU-relative latencies grow.  ...  As DRAM access latencies approach a thousand instruction-execution times and onchip caches grow to multiple megabytes, it is not clear that conventional cache structures continue to be appropriate.  ...  In the DASC cache, a block can reside in only a limited number of locations.  ... 
doi:10.1145/342001.339660 fatcat:ffrv4g6i45fgzfjwjnntdqugje

A fully associative software-managed cache design

Erik G. Hallnor, Steven K. Reinhardt
2000 Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00  
is kept low by the now-common presence of a secondary cache.  ...  a conventional cache as these CPU-relative latencies grow. 1.  ...  In the DASC cache, a block can reside in only a limited number of locations.  ... 
doi:10.1145/339647.339660 fatcat:zxmsohyahbh37m37qa5po3qhsa

Improving Power Efficiency with an Asymmetric Set-Associative Cache [chapter]

Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi
2004 High Performance Memory Systems  
Set-associativity in these caches helps programs avoid performance problems due to cache mapping conflicts.  ...  Current set associative caches are symmetric in the sense that each way has the same number of cache lines.  ...  Group associative caches [18] and DASC (Direct-mapped Access Set-associative Check) caches [22] are examples in this category.  ... 
doi:10.1007/978-1-4419-8987-1_6 fatcat:lfvpyrqm4bgd7bmmzsv6im6dd4

WOCC 2020 Program

2020 2020 29th Wireless and Optical Communications Conference (WOCC)  
: A Privacy-Protected Data Access System with Cache Mechanism for Smartphones Wenyun Dai (Fairleigh Dickinson University, USA), Longbin Chen (IBM, USA), Ana Wu (Butterfly Network Inc, USA), Md L Ali  ...  Yaoqing Liu (Fairleigh Dickinson University, USA), Laurent Njilla (Air Force Research Laboratory, USA), Anthony Dowling (Clarkson University, USA), Wan Du (University of California, Merced, USA) 68 DASC  ... 
doi:10.1109/wocc48579.2020.9114933 fatcat:sdkhci5apzchbabpiud3vzapnu

Botanische Gesellschaften, Vereine, Congresse etc

1896 Plant Systematics and Evolution  
Dasc. M. Herr Prof. R. v. Wettstein iabersendet eine Ab- hand]3. Die Angabe N.  ...  Caches~iriana Gay, ~.0. H. Olym- pica Gay. Subsect. 2. Flores tetrameri. 21. ~ pol~gama Gay. Bot nisehe @esellsoh ften, Vereine, Gongresse eto, I.  ... 
doi:10.1007/bf01795487 fatcat:qzva27bphvcg3m7fbbi43qrkoy

Table of contents

2020 2020 IEEE 36th International Conference on Data Engineering Workshops (ICDEW)  
Adjustment toward Fair Proof-of-Work Blockchains 1 Reiki Kanda (Tokyo Institute of Technology) and Kazuyuki Shudo (Tokyo Institute of Technology) International Workshop on Data-Driven Smart Cities (DASC  ...  Fent (Technische Universität München), Michael Jungmair (Technische Universität München), Andreas Kipf (Technische Universität München), and Thomas Neumann (Technische Universität München) Selective Caching  ... 
doi:10.1109/icdew49219.2020.00004 fatcat:w6s2hxdyinhvbfy34nu26q2gpm

Capturing dynamic memory reference behavior with adaptive cache topology

Jih-Kwon Peir, Yongjoon Lee, Windsor W. Hsu
1998 Proceedings of the eighth international conference on Architectural support for programming languages and operating systems - ASPLOS-VIII  
DASC) cache [21] , the difference-bit directory [12] , and the alternative tag path method [17] .  ...  cache sets.  ... 
doi:10.1145/291069.291053 dblp:conf/asplos/PeirLH98 fatcat:hmfosgnqwzap5fg7oihs4xniee

Capturing dynamic memory reference behavior with adaptive cache topology

Jih-Kwon Peir, Yongjoon Lee, Windsor W. Hsu
1998 SIGPLAN notices  
DASC) cache [21] , the difference-bit directory [12] , and the alternative tag path method [17] .  ...  cache sets.  ... 
doi:10.1145/291006.291053 fatcat:5mmburn4qfhuthucow5j22jfxi
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