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Fault tolerant clockless wave pipeline design

T. Feng, B. Jin, J. Wang, N. Park, Y. B. Kim, F. Lombardi
2004 Proceedings of the first conference on computing frontiers on Computing frontiers - CF'04  
The specific architectural model investigated in this paper is the two-phase clockless asynchronous wave pipeline [10] which is ideally supposed to yield the theoretical maximum of performance.  ...  In practice, the request signal is very sensitive and vulnerable to electronic crosstalk noise, and this problem has become exteremely stringent for the ultra-high density integrated circuits today.  ...  The specific architectural model investigated in this paper is the two-phase clockless asynchronous wave pipeline [10] which is ideally supposed to yield the theoretical maximum of performance.  ... 
doi:10.1145/977091.977142 dblp:conf/cf/FengJWPKL04 fatcat:t7zxyfflkvcqbbfbceqgtxukzu

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

Jiang Xu, Wayne Wolf, Wei Zhang
2009 IEEE Micro  
An H.264 HDTV decoder implementation requires low cost, low power, and high performance.  ...  DWP provides a larger design space for asynchronous NoCs.  ... 
doi:10.1109/mm.2009.40 fatcat:wli4al26qvevppfzfldp5g2opi

Investigation of transient fault effects in synchronous and asynchronous Network on Chip router

Pooria M. Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid Reza Zarandi
2011 Journal of systems architecture  
The effort has been accomplished by employing fault injector signal (FIS) in asynchronous design and synchronous one.  ...  Different fault models such as Crosstalk, SEU, and SET have been applied in both architectures to evaluate their robustness. Glitch fault model has also been injected through the asynchronous scheme.  ...  However, the high percentage of failure rate of SET fault models is important in asynchronous design.  ... 
doi:10.1016/j.sysarc.2010.10.003 fatcat:xmktb2c3bbfolist73r3oimdba

Investigation of Transient Fault Effects in an Asynchronous NoC Router

Pooria M. Yaghini, Ashkan Eghbal, H. Pedram, H.R. Zarandi
2010 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing  
Although asynchronous designs seem inherently fault-tolerant due to applying handshaking signals, up to 56% of the injected faults result in failure, and about 43% of injected faults are overwritten before  ...  This paper presents Investigation of Transient Fault Effects in an asynchronous NoC router.  ...  The effects of injected faults in asynchronous designs have been introduced in this effort. Furthermore, SET and crosstalk fault models must be more considered in switch component.  ... 
doi:10.1109/pdp.2010.21 dblp:conf/pdp/YaghiniEPZ10 fatcat:7r5ahag52vehdowebspa72vbbe

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Naoya ONIZAWA, Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Masashi IMAI, Tomohiro YONEDA, Takahiro HANYU
2014 IEICE transactions on information and systems  
Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os.  ...  The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial  ...  In future work, we plan to fabricate the proposed link by specifying design parameters based on the proposed model and measure the performance with asynchronous NoCs.  ... 
doi:10.1587/transinf.e97.d.1546 fatcat:xkde57mxwzfyxlrja2jggpm6iu

Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits

S JAYANTHY, M C BHUVANESWARI
2015 Sadhana (Bangalore)  
faults in asynchronous sequential circuits.  ...  In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed.  ...  Asynchronous circuits have high performance gains and low power when compared to their synchronous counterparts.  ... 
doi:10.1007/s12046-014-0302-1 fatcat:idtckssvpfhijc2ykujxwccgmu

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission

G. YAN, Y. HAN, X. LI, H. LIU
2008 IEICE transactions on electronics  
Crosstalk delay within an on-chip bus can induces a severe transmission performance penalty. Bus-grouping Asynchronous Transmission (BAT) scheme is proposed to mitigate the performance degradation.  ...  signals from crosstalk and optimize the routing area overhead.  ...  This work can be done in early design phases of chip design process, and the locality characteristic can be used to guide high performance bus fabrication.  ... 
doi:10.1093/ietele/e91-c.10.1690 fatcat:3zqlerzpd5c6difhcsmi7ocvjm

Asynchronous Current Mode Serial Communication

Rostislav Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar
2010 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation.  ...  The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge.  ...  Salach for performing the Cadence simulations of the current and voltage mode circuits.  ... 
doi:10.1109/tvlsi.2009.2020859 fatcat:mprjajai5bcjdfox6sldj63gpe

RasP: An Area-efficient, On-chip Network

Simon Hollis, Simon W. Moore
2006 2006 International Conference on Computer Design  
We present RasP, our asynchronous on-chipnetwork, which uses high-speed pulse-based signalling techniques.  ...  We also show that it compares favourably in performance and area to Bainbridge et al.'s Chain interconnect.  ...  Chain, unfortunately, suffers performance penalties: asynchronous designs are based on C-elements, state-holding multiple-input gates.  ... 
doi:10.1109/iccd.2006.4380795 dblp:conf/iccd/HollisM06 fatcat:r6maweo7vbf3lcpdxgiltudiki

OCDMA over WDM PON-solution path to gigabit-symmetric FTTH

K. Kitayama, Xu Wang, Naoya Wada
2006 Journal of Lightwave Technology  
The system architecture and its operation principle, code design, optical en/decoding, using a long superstructured fiber Bragg grating (SSFBG) en/decoder, and its system performance will be described.  ...  The system architecture and the WDM interchannel crosstalk will be studied.  ...  In the long run, the service demands will further progress toward high bit rate and customization.  ... 
doi:10.1109/jlt.2006.871030 fatcat:ctycqn5cqraxdfte74fmufxl4i

The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication

Yan Liu, Lu Ding, Yu Cao, Dongyang Wan, Guanghui Yuan, Baohu Huang, Aaron Voon-Yew Thean, Ting Mei, Thirumalai Venkatesan, Christian A. Nijhuis, Soojin Chua
2020 IEEE Photonics Journal  
This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip.  ...  global wires for the asynchronous communication.  ...  Acknowledgements This research was supported by National Research Foundation Singapore project of Integration of Electrically Driven Plasmonic Components in High Speed (NRF2016_CRP001_111).  ... 
doi:10.1109/jphot.2020.3024119 fatcat:ozxivytjvrdrvdqctgoczm7wjy

A Decoupling Technique for Efficient Timing Analysis of VLSI Interconnects With Dynamic Circuit Switching

Y. Eo, S. Shin, W.R. Eisenstadt, J. Shim
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal transients are strongly correlated with the input switching patterns.  ...  Maintaining a high-level of VLSI circuit-signal integrity becomes one of the crucial circuit-design issues [7] - [48] , particularly, in today's high-performance VLSI circuits based on ultra deep submicron  ...  In high-performance VLSI circuits, signal integrity deteriorates during circuit switching or signal propagation [4] - [6] .  ... 
doi:10.1109/tcad.2004.831571 fatcat:hdujlg5dhzfi3ptxkmw2p32ylm

Development of a new distributed hybrid seismic-electrical data acquisition station based on system–on-a-programmable-chip technology

Qisheng Zhang, Wenhao Li, Feng Guo, Zhenzhong Yuan, Shuaiqing Qiao, Qimao Zhang
2019 Geoscientific Instrumentation Methods and Data Systems Discussions  
to enable high-speed stable data transmission.  ...  to enhance the precision of synchronous acquisition was studied in depth.  ...  of the noise in the short-circuited channel, indicating that the level of crosstalk between the channels satisfies design requirements.  ... 
doi:10.5194/gi-2019-12 fatcat:pnpcl4c42veblaanjquxktvkvq

Crosstalk performance of coherent time-addressed photonic CDMA networks

D.D. Sampson, M. Calleja, R.A. Griffin
1998 IEEE Transactions on Communications  
We report a theoretical investigation of the crosstalk performance of photonic code-division multiple-access (CDMA) networks that are based on coherent matched filtering of optical pulses.  ...  We give guidelines for the selection of codes in coherent matched filtering, and give a code set that produces low crosstalk.  ...  We consider in detail the design and performance of codes in coherent matched filtering.  ... 
doi:10.1109/26.662639 fatcat:qwvyokrox5eehc6fwyjn3sylpm

Long Time Field Emission of Pt/MWCNT Hybrid nanowire for Electron Gun

Wenqi Zhang, Lixin Dong, Yajing Shen, Zhan Yang
2019 2019 International Conference on Manipulation, Automation and Robotics at Small Scales (MARSS)  
enable high-speed stable data transmission.  ...  We designed the data transmission protocol for the acquisition station and developed independently an improved low-voltage differential signaling data transmission technology.  ...  (−128 dB) in the seismic channel in Fig. 13 , indicating that the level of crosstalk between the channels satisfies design requirements.  ... 
doi:10.1109/marss.2019.8860949 fatcat:vqy7mfrhm5cs5gmfq6llyrbe74
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