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Crossing Minimization and Layouts of Directed Hypergraphs with Port Constraints [chapter]

Markus Chimani, Carsten Gutwenger, Petra Mutzel, Miro Spönemann, Hoi-Ming Wong
2011 Lecture Notes in Computer Science  
In this paper, we consider the problem of drawing directed hypergraphs with (and without) port constraints, which cover multiple real-world graph drawing applications like data flow diagrams and electric  ...  We show how to adopt this idea for hypergraphs with given port constraints, obtaining an upward-planar representation (UPR) of the input hypergraph where crossings are modeled by dummy nodes.  ...  In this paper we consider the problem of drawing directed hypergraphs with port constraints. Basic definitions on hypergraphs are given in Sect. 1.1, and port constraints are introduced in Sect. 1.2.  ... 
doi:10.1007/978-3-642-18469-7_13 fatcat:2efprs4nvrhojfoy4gdnt5uwsi

A Mixed-Integer Program for Drawing Orthogonal Hyperedges in a Hierarchical Hypergraph

Gregory Fridman, Yuri Vasiliev, Vlada Puhkalo, Vladimir Ryzhov
2022 Mathematics  
The hyperedges of a hypergraph are assumed to be multi-source and multi-target, and vertices are depicted as rectangles with ports on their top and bottom sides.  ...  This paper presents a new formulation and solution of a mixed-integer program for the hierarchical orthogonal hypergraph drawing problem, and the number of hyperedge crossings is minimized.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/math10050689 fatcat:hdjuwg45kfbp3ic5gfajuyra6a

Complexity of Finding Non-Planar Rectilinear Drawings of Graphs [chapter]

Ján Maňuch, Murray Patterson, Sheung-Hung Poon, Chris Thachuk
2011 Lecture Notes in Computer Science  
Minimization and Layouts of Directed Hypergraphs with Port Constraints p. 141 Drawing Graphs on a Smartphone p. 153 Topology-Driven Force-Directed Algorithms p. 165 On Graphs Supported by Line  ...  Resolution of Graphs p. 62 Plane Drawings of Queue and Deque Graphs p. 68 An Experimental Evaluation of Multilevel Layout Methods p. 80 Orthogonal Graph Drawing with Flexibility Constraints  ... 
doi:10.1007/978-3-642-18469-7_28 fatcat:pxln4k6bzbhxrlde4iufrtt74u

Semi-bipartite Graph Visualization for Gene Ontology Networks [chapter]

Kai Xu, Rohan Williams, Seok-Hee Hong, Qing Liu, Ji Zhang
2010 Lecture Notes in Computer Science  
16:00 Drawing Directed Graphs Clockwise, Christian Pich 16:00 -16:25 An Improved Algorithm for the Metro-Line Crossing Minimization Problem, Martin Nöllenburg 16:25 -16:60 Layout with Circular and Other  ...  In this paper we present extensions of the well-known hierarchical layout approach, originally suggested by Sugiyama et al., to support port constraints, hyperedges, and compound graphs in order to layout  ... 
doi:10.1007/978-3-642-11805-0_24 fatcat:724qxxufdzgthfzrovmnj4nzky

Algorithms for the Hypergraph and the Minor Crossing Number Problems

Markus Chimani, Carsten Gutwenger
2015 Journal of Graph Algorithms and Applications  
We consider the problems of hypergraph and minor crossing minimization, and point out relationships between these two problems that have not been exploited before.  ...  Based thereon, we present the first planarization-based heuristics for hypergraph and minor crossing minimization.  ...  ., for crossing minimal layouts of electrical circuits [4] . Consider Figure 1 .  ... 
doi:10.7155/jgaa.00353 fatcat:wqc2cy75gfdljl4od7y2dy4uha

A Novel Grid-Based Visualization Approach for Metabolic Networks with Advanced Focus&Context View [chapter]

Markus Rohrschneider, Christian Heine, André Reichenbach, Andreas Kerren, Gerik Scheuermann
2010 Lecture Notes in Computer Science  
Our approach supports bundled edge routes heuristically minimizing a given cost function based on the number of bends, the number of edge crossings and the density of edges within a bundle.  ...  In this paper, we introduce a novel approach to generate an interactive layout of such a metabolic network taking its hierarchical structure into account and present methods for navigation and exploration  ...  In this hypergraph model, each substance is represented by a node of the graph, and each reaction by a (directed) hyperedge connecting the input node set-substrates-with the output node set-products-of  ... 
doi:10.1007/978-3-642-11805-0_26 fatcat:6rqd3f3yabebxeeifjj43m26le

Algebraic Methods for Counting Euclidean Embeddings of Rigid Graphs [chapter]

Ioannis Z. Emiris, Elias P. Tsigaridas, Antonios E. Varvitsiotis
2010 Lecture Notes in Computer Science  
Our approach supports bundled edge routes heuristically minimizing a given cost function based on the number of bends, the number of edge crossings and the density of edges within a bundle.  ...  In this paper, we introduce a novel approach to generate an interactive layout of such a metabolic network taking its hierarchical structure into account and present methods for navigation and exploration  ...  In this hypergraph model, each substance is represented by a node of the graph, and each reaction by a (directed) hyperedge connecting the input node set-substrates-with the output node set-products-of  ... 
doi:10.1007/978-3-642-11805-0_19 fatcat:cdtf6cwv3vdmna24yln6dtzfoq

MetroSets: Visualizing Sets as Metro Maps [article]

Ben Jacobsen, Markus Wallinger, Stephen Kobourov, Martin Nollenburg
2020 arXiv   pre-print
MetroSets is based on a modular 4-step pipeline which constructs and optimizes a path-based hypergraph support, which is then drawn and schematized using metro map layout algorithms.  ...  We model a given set system as a hypergraph ℋ = (V, 𝒮), consisting of a set V of vertices and a set 𝒮, which contains subsets of V called hyperedges.  ...  We also thank Miranda Rintoul for her help with the experimental analysis.  ... 
arXiv:2008.09367v1 fatcat:etimrbie3jeglfeh6a7xisnbsq

Fast hypergraph partition

A. B. Kahng
1989 Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89  
The method is provably good and, in particular, obtains optimum results for "difficult" inputs, i.e., hypergraphs with smaller than expected minimum cutsize.  ...  Computational results for a wide range of inputs are also discussed.  ...  In practice, chips have a bounded number of pins, VLSI standard cells have a small, bounded number of ports, and so forth.  ... 
doi:10.1145/74382.74524 dblp:conf/dac/Kahng89 fatcat:6byuy7hzi5ct7p44ljqux35hva

Diagonal Component Expansion for Flow-Layer Placement of Flow-Based Microfluidic Biochips

Brian Crites, Karen Kong, Philip Brisk
2017 ACM Transactions on Embedded Computing Systems  
Continuous flow-based microfluidic devices have seen a huge increase in interest because of their ability to automate and miniaturize biochemistry and biological processes, as well as their promise of  ...  The major hurdle in the adoption of these types of devices is in the design, which is largely done by hand using tools such as AutoCAD or SolidWorks, which require immense domain knowledge and are hard  ...  The problem of simultaneous mVLSI planarization and layout with minimal switch insertion is identical to the problem of graph embedding while minimizing the number of edge crossings; the reduction inserts  ... 
doi:10.1145/3126529 fatcat:kjs3yahtkbh3bgkienxnmopyjm

A technique for low energy mapping and routing in network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha
2005 Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05  
NoC design with mesh based topologies requires mapping of cores to router ports, and routing of traffic traces such that the bandwidth and latency constraints are satisfied.  ...  We present a novel automated design technique that solves the mesh based NoC design problem with an objective of minimizing the communication energy.  ...  Mbps of traffic bandwidth flowing in the output direction for any port of the router.  ... 
doi:10.1145/1077603.1077695 dblp:conf/islped/SrinivasanC05 fatcat:ke23n66iybh77lvt6k3jcdzgmq

A technique for low energy mapping and routing in network-on-chip architectures

K. Srinivasan, K.S. Chatha
2005 ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.  
NoC design with mesh based topologies requires mapping of cores to router ports, and routing of traffic traces such that the bandwidth and latency constraints are satisfied.  ...  We present a novel automated design technique that solves the mesh based NoC design problem with an objective of minimizing the communication energy.  ...  Mbps of traffic bandwidth flowing in the output direction for any port of the router.  ... 
doi:10.1109/lpe.2005.195552 fatcat:gembbtigenaqpdsdczztfb3a54

Scalable Visualization of Semantic Nets using Power-Law Graphs

Ajaz Hussain, Khalid Latif, Aimal Tariq Rextin, Amir Hayat, Masoon Alam
2014 Applied Mathematics & Information Sciences  
The core concept is to partition the node set of a graph into power and non-power nodes and to apply a modified force-directed method that emphasizes the power nodes which results in establishing local  ...  Results show that our technique handles very large scale semantic nets with a substantial performance improvement while producing aesthetically pleasant layouts.  ...  Acknowledgement The authors acknowledge the financial support by the ICT R&D Fund (Pakistan) project on Semantic Search and Filtering.  ... 
doi:10.12785/amis/080145 fatcat:qddxmvxvhvbunai4lgr6vzjl3a

A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications

Daniela Sánchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Robert Wille, Wolfgang Ecker
2022 ACM Transactions on Design Automation of Electronic Systems  
Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market.  ...  To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing.  ...  ACKNOWLEDGMENTS The work described herein is partly funded by the German Federal Ministry for Economic Afairs and Energy (BMWi) as part of the research project ProgressivKI (19A21006C).  ... 
doi:10.1145/3543853 fatcat:halhg7zwgvdpjkzf7g7ctxzuby

Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation

Bailey Miller, Frank Vahid, Tony Givargis, Philip Brisk
2014 ACM Transactions on Reconfigurable Technology and Systems  
ACM Reference Format: Bailey Miller, Frank Vahid, Tony Givargis, and Philip Brisk. 2014. Graph-based approaches to placement of processing element networks on FPGAs for physical model simulation.  ...  Additionally, complex models that could not previously be routed due to complexity were made routable when using placement constraints.  ...  A PE consists of an output port, an input port connected directly to the output of other PEs in the network, an instruction RAM containing microcoded control words, and a pipelined datapath.  ... 
doi:10.1145/2629521 fatcat:2ewp42jk4vdypkjqeaxv2j3tge
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