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Counterexample- and Simulation-Guided Floating-Point Loop Invariant Synthesis [chapter]

Anastasiia Izycheva, Eva Darulova, Helmut Seidl
2020 Lecture Notes in Computer Science  
AbstractWe present an automated procedure for synthesizing sound inductive invariants for floating-point numerical loops.  ...  Such invariants are a prerequisite for reasoning about the safety and roundoff errors of floating-point programs.  ...  Simulation The synthesis starts by simulating the loop execution.  ... 
doi:10.1007/978-3-030-65474-0_8 fatcat:g62rmena2ranrmrobp6jmwqhde

Verified lifting of stencil computations

Shoaib Kamil, Alvin Cheung, Shachar Itzhaky, Armando Solar-Lezama
2016 SIGPLAN notices  
The technique is sound and mostly automated, and leverages counter-example guided inductive synthesis (CEGIS) to find provably correct translations.  ...  This paper demonstrates a novel combination of program synthesis and verification to lift stencil computations from low-level Fortran code to a high-level summary expressed using a predicate language.  ...  Acknowledgements This work was partially supported by DOE Office of Science Awards DE-SC0005288 and DE-SC0008923.  ... 
doi:10.1145/2980983.2908117 fatcat:wxgagts4ajbt3lpxstczysqjyi

Verified lifting of stencil computations

Shoaib Kamil, Alvin Cheung, Shachar Itzhaky, Armando Solar-Lezama
2016 Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI 2016  
The technique is sound and mostly automated, and leverages counter-example guided inductive synthesis (CEGIS) to find provably correct translations.  ...  This paper demonstrates a novel combination of program synthesis and verification to lift stencil computations from low-level Fortran code to a high-level summary expressed using a predicate language.  ...  Acknowledgements This work was partially supported by DOE Office of Science Awards DE-SC0005288 and DE-SC0008923.  ... 
doi:10.1145/2908080.2908117 dblp:conf/pldi/KamilCIS16 fatcat:siayelnp4vb4jogvfxdsso7oxm

Counterexample guided inductive optimization based on satisfiability modulo theories

Rodrigo F. Araújo, Higo F. Albuquerque, Iury V. de Bessa, Lucas C. Cordeiro, João E. Chaves Filho
2018 Science of Computer Programming  
This paper describes three variants of a counterexample guided inductive optimization (CEGIO) approach based on Satisfiability Modulo Theories (SMT) solvers.  ...  CEGIO is able to successfully optimize a wide range of functions, including non-linear and non-convex optimization problems based on SMT solvers, in which data provided by counterexamples are employed  ...  Acknowledgments The authors thank the financial support of FundaÃgÃčo de Amparo Ãȃ Pesquisa do Estado do Amazonas (FAPEAM), Brazil, the Brazilian National Research Council (CNPq), and the Coordination  ... 
doi:10.1016/j.scico.2017.10.004 fatcat:6ogg5lwxargzrlg3hpmhxtqhqm

Counterexample Guided Inductive Optimization [article]

Rodrigo F. Araujo, Higo F. Albuquerque, Iury V. de Bessa, Lucas C. Cordeiro, Joao Edgar C. Filho
2017 arXiv   pre-print
This paper describes three variants of a counterexample guided inductive optimization (CEGIO) approach based on Satisfiability Modulo Theories (SMT) solvers.  ...  CEGIO is able to successfully optimize a wide range of functions, including non-linear and non-convex optimization problems based on SMT solvers, in which data provided by counterexamples are employed  ...  This class of techniques is defined here as counterexample guided inductive optimization (CEGIO), which is inspired by the syntax-guided synthesis (SyGuS) to perform inductive generalization based on counterexamples  ... 
arXiv:1704.03738v1 fatcat:v5i4vxl6qnbmhbqtcmvefys6ne

How testing helps to diagnose proof failures

Guillaume Petiot, Nikolai Kosmatov, Bernard Botella, Alain Giorgetti, Jacques Julliand
2018 Formal Aspects of Computing  
function or a loop, and lack of time or simply incapacity of the prover to finish a particular proof.  ...  This work proposes a methodology where test generation helps to identify the reason of a proof failure and to exhibit a counterexample clearly illustrating the issue.  ...  The authors thank the FRAMA-C and PATHCRAWLER teams for providing the tools and support.  ... 
doi:10.1007/s00165-018-0456-4 fatcat:5pc3j6f6vveqdfswn35gymoeqa

Automated Verification and Synthesis of Embedded Systems using Machine Learning [article]

Lucas Cordeiro
2017 arXiv   pre-print
Reliability issues, in the development of micro-grids and cyber-physical systems, are then considered, as a prominent verification and synthesis application.  ...  The present research discusses challenges, problems, and recent advances to ensure correctness and timeliness regarding embedded systems.  ...  programs, especially for those that contain intensive floating-point arithmetic and dynamic memory allocation.  ... 
arXiv:1702.07847v2 fatcat:icus3c6bovbqvineb5n26ydcva

Automated Formal Synthesis of Digital Controllers for State-Space Physical Plants [article]

Alessandro Abate, Iury Bessa, Dario Cattaruzza, Lucas Cordeiro, Cristina David, Pascal Kesseli, Daniel Kroening, Elizabeth Polgreen
2017 arXiv   pre-print
Our approach has two stages, leveraging counterexample guided inductive synthesis (CEGIS) and reachability analysis.  ...  We present a sound and automated approach to synthesize safe digital feedback controllers for physical plants represented as linear, time invariant models.  ...  In both cases, the SDP solver uses floating-point arithmetic and soundness is checked by bounding the error.  ... 
arXiv:1705.00981v2 fatcat:dntpzupolfhwrp6aeixugaztw4

Automated Formal Synthesis of Digital Controllers for State-Space Physical Plants [chapter]

Alessandro Abate, Iury Bessa, Dario Cattaruzza, Lucas Cordeiro, Cristina David, Pascal Kesseli, Daniel Kroening, Elizabeth Polgreen
2017 Lecture Notes in Computer Science  
Our counterexample guided inductive synthesis (CEGIS) approach has two phases: We synthesize a static feedback controller that stabilizes the system but that may not be safe for all initial conditions.  ...  Safety is then verified either via BMC or abstract acceleration; if the verification step fails, a counterexample is provided to the synthesis engine and the process iterates until a safe controller is  ...  In both cases, the SDP solver uses floating-point arithmetic and soundness is checked by bounding the error.  ... 
doi:10.1007/978-3-319-63387-9_23 fatcat:dwbqyizbxrha7chzmbkvxfgaxi

Automated and Formal Synthesis of Neural Barrier Certificates for Dynamical Models [chapter]

Andrea Peruffo, Daniele Ahmed, Alessandro Abate
2021 Lecture Notes in Computer Science  
AbstractWe introduce an automated, formal, counterexample-based approach to synthesise Barrier Certificates (BC) for the safety verification of continuous and hybrid dynamical models.  ...  The approach is underpinned by an inductive framework: this is structured as a sequential loop between a learner, which manipulates a candidate BC structured as a neural network, and a sound verifier,  ...  We leverage a CounterExample-Guided Inductive Synthesis (CEGIS) procedure [31] , which is structured as an inductive loop between a Learner and a Verifier (cf. Fig. 1) .  ... 
doi:10.1007/978-3-030-72016-2_20 fatcat:bpbllc6omzedhowy3gvwextkjq

Reveal: A Formal Verification Tool for Verilog Designs [chapter]

Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah
2008 Lecture Notes in Computer Science  
Reveal employs counterexample-guided abstraction refinement, or CEGAR, and is suitable for verifying the complex control logic of designs with wide datapaths.  ...  The Reveal system allows some user control over the abstraction and refinement steps.  ...  We verified the property that the Decoder activates the corresponding decode unit (Integer versus Floating Point) when the instruction is confined to a set of 6 integer and floating point op-codes.  ... 
doi:10.1007/978-3-540-89439-1_25 fatcat:33f3d7qdhbasdlyikpueucgpza

Property Directed Equivalence via Abstract Simulation [chapter]

Grigory Fedyukovich, Arie Gurfinkel, Natasha Sharygina
2016 Lecture Notes in Computer Science  
The key idea behind our simulation synthesis is to drive construction of both αP and ρ by the safe inductive invariants of P , thus guaranteeing the property preservations by the results.  ...  Model checkers for the programs with unbounded (and possibly nested) loops reduce the verification tasks to finding safe inductive invariants.  ...  The most distinguishing feature of ASSI compared to SimAbs, is that it guides the whole process of edge-simulation synthesis by invariants.  ... 
doi:10.1007/978-3-319-41540-6_24 fatcat:3xjyuyi2cjbfzdunq2i7peay4e

Boolean Satisfiability Solvers and Their Applications in Model Checking

Yakir Vizel, Georg Weissenbacher, Sharad Malik
2015 Proceedings of the IEEE  
SAT has many applications in electronic design automation (EDA), notably in synthesis and verification.  ...  and their extensions.  ...  Egly, and the anonymous reviewers for their helpful comments.  ... 
doi:10.1109/jproc.2015.2455034 fatcat:xl5yuqw53bbgrjf653fn3rlbwq

Data-driven equivalence checking

Rahul Sharma, Eric Schkufza, Berkeley Churchill, Alex Aiken
2013 Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications - OOPSLA '13  
We present a data driven algorithm for equivalence checking of two loops. The algorithm infers simulation relations using data from test runs.  ...  Once a candidate simulation relation has been obtained, off-the-shelf SMT solvers are used to check whether the simulation relation actually holds.  ...  Acknowledgments We thank George Necula, Jan Vitek, and the anonymous reviewers for their constructive comments.  ... 
doi:10.1145/2509136.2509509 dblp:conf/oopsla/0001SCA13 fatcat:gq6o6vl6anconhxxviqblguski

Language support for dynamic, hierarchical data partitioning

Sean Treichler, Michael Bauer, Alex Aiken
2013 Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications - OOPSLA '13  
We present a data driven algorithm for equivalence checking of two loops. The algorithm infers simulation relations using data from test runs.  ...  Once a candidate simulation relation has been obtained, off-the-shelf SMT solvers are used to check whether the simulation relation actually holds.  ...  Acknowledgments We thank George Necula, Jan Vitek, and the anonymous reviewers for their constructive comments.  ... 
doi:10.1145/2509136.2509545 dblp:conf/oopsla/TreichlerBA13 fatcat:tdcyzqw3qzfrvcoumlwrxxa5du
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