Filters








1,810 Hits in 12.0 sec

Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation

Peipei Hao, Shuming Chen, Pengcheng Huang, Jianjun Chen, Bin Liang
2017 Science China Information Sciences  
Acknowledgements This work was supported by National Natural Science Foundation of China (Grant Nos. 61376109, 61434007).  ...  In this paper, a cost-effective SETtolerant CDN design by mitigating SET propagation is proposed.  ...  It has been shown that clock distribution networks (CDNs) are becoming increasingly vulnerable to transient faults known as single event transients (SETs), owing to technology scaling [1] .  ... 
doi:10.1007/s11432-016-9041-5 fatcat:dg3bkdqsvbecvbeumxszvjvqum

Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits

S. Almukhaizim, Feng Shi, E. Love, Y. Makris
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Asynchronous burst-mode circuits, soft errors, soft-error mitigation, soft-error susceptibility, soft-error tolerance.  ...  subset of transient errors.  ...  the clock network in synchronous designs).  ... 
doi:10.1109/tvlsi.2009.2014381 fatcat:huzpal47ifbkda37jnuucttkx4

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

Stefan Biereigel, Szymon Kulis, Paulo Moreira, Alexander Kölpin, Paul Leroux, Jeffrey Prinzie
2021 Electronics  
Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.52/mg as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5Grad  ...  The circuit is designed to operate at reference clock frequencies from 40–320 or at data rates from 40Mbps–320Mbps and displays a jitter performance of 520 with a power dissipation of only 11 and an FOM  ...  Acknowledgments: The authors would like to acknowledge Dipan Kar for their contribution to the LC DCO design. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics10222741 fatcat:5wrqurtw4rchhad4id5obr5euq

An accurate flip-flop selection technique for reducing logic SER

Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
While a myriad of techniques have been proposed to mitigate the effects of soft errors, system designers must ensure that the application of these solutions does not come at the expense of other design  ...  In particular, the effects of these errors on logic nodes are predicted to play an increasingly large role in determining the overall failure rate of future VLSI chips.  ...  If the device is part of a combinational logic gate, the charge injected could trigger the generation of a single event transient (SET).  ... 
doi:10.1109/dsn.2008.4630081 dblp:conf/dsn/HillLS08 fatcat:mpfilufhqfeytctiekvm5ut2am

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Oliver Schrape, Marko Andjelkovic, Anselm Breitenreiter, Steffen Zeidler, Alexey Balashov, Milos Krstic
2021 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET  ...  Index Terms-Single event effect, fault tolerance, triple modular redundancy, ASIC design flow, radhard design.  ...  The critical soft SEEs are the Single Event Transients (SETs) and the Single Event Upsets (SEUs).  ... 
doi:10.1109/tcsi.2021.3109080 fatcat:3fpd7qbqungmnpai7ptb5heglm

A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems [article]

Shashikiran Venkatesha, Ranjani Parthasarathi
2022 arXiv   pre-print
The Through silicon via based 3D Network on chip is the prospective solution for integrating many cores on single die.  ...  The article presents a congregation of concepts illustrated one after the other for a better understanding of damages caused by radiation, relevant fault models, and effects of faults.  ...  Single event transients and single event upsets are detected by transition detector.  ... 
arXiv:2203.07830v1 fatcat:dsbx3o4v3femhi5d6kfrurzuoi

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Hao Wu, Gang Jin, Yiqi Zhuang, Wenrui Cao, Lei Bai
2021 IEICE Electronics Express  
A power-efficient Single Event Upset (SEU) -tolerant pulsetriggered flip-flop design is presented.  ...  The SEU tolerance is evaluated by means of SEU cross section, which is significantly lower than conventional D flip-flop.  ...  It has been reported that flip-flops and last sections of clock distribution network that directly drive flip-flops account for 90% of the clock system power [14, 15, 16] .  ... 
doi:10.1587/elex.18.20210312 fatcat:7haivlz2xjg3xketrtgxbfpq2e

Design of a soft-error robust microprocessor

Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
2009 Microelectronics Journal  
inversões de bits; e pulsos transientes Single Event Transients (SETs) em qualquer nó do circuito.  ...  inversões de bits; e pulsos transientes Single Event Transients (SETs) em qualquer nó do circuito.  ...  Fault Injection by Simulation Fault injection experiments were performed through the post-layout gate-level simulation discussed in section 5.1.1. The goal of this simulation experiment is to verify  ... 
doi:10.1016/j.mejo.2008.10.001 fatcat:pfqera6sdnbshgwa3n7ptqh76u

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC

Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang
2011 2011 IEEE Computer Society Annual Symposium on VLSI  
This paper presents a low-overhead hardware-software collaborated method, called SENoC, to dynamically mitigate soft errors on MPSoCs using an on-chip sensor network.  ...  To maximize the performance of soft-error tolerant MPSoCs, a hybrid scheduling scheme is proposed to effectively manage applications and resources under uncertainties.  ...  ACKNOWLEDGEMENT This work is supported by RGC, Hong Kong SAR.  ... 
doi:10.1109/isvlsi.2011.48 dblp:conf/isvlsi/LiuXWWZYWNW11 fatcat:kdxseofyejanbgfni5xavsm5bm

Fault-tolerant Distributed Systems in Hardware

Danny Dolev, Matthias Függer, Christoph Lenzen, Ulrich Schmid, Andreas Steininger
2015 Bulletin of the European Association for Theoretical Computer Science  
By means of problems related to clock generation and distribution, we show that (i) design and analysis techniques from distributed computing can provide new and provably correct mission critical hardware  ...  We advocate to act on this observation and treat fault-tolerant hardware design as the task of devising suitable distributed algorithms.  ...  Jang and Martin [53] adapted this method to QDI designs and applied it to build a microcontroller tolerating certain transient faults [54] , in particular, single-event upsets (SEUs), where a state-holding  ... 
dblp:journals/eatcs/DolevFLSS15 fatcat:lkyml64cujhdfdblc2qcboenby

Designing fault-tolerant network-on-chip router architecture

Ashkan Eghbal, Pooria M. Yaghini, H. Pedram, H. R. Zarandi
2010 International journal of electronics (Print)  
(b) Area consumption in different designs. Table 1 . 1 Fault injection distribution.  ...  The FISs are distributed through the main components based on their complexities. The effects of single faults are taken into account in this experiment.  ... 
doi:10.1080/00207217.2010.512016 fatcat:tbx3qssdg5dzpclo64hwe7i5ny

Architecture implications of pads as a scarce resource

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2014 SIGARCH Computer Architecture News  
In this paper, we develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation  ...  is and will remain a critical problem for architects and circuit designers alike.  ...  Acknowledgments This work is supported by NSF grant CNS-0916908 and MCDA-0903471, and DARPA MTO under contract no.HR0011-13-C-0022.  ... 
doi:10.1145/2678373.2665728 fatcat:kkwbrdtdrjasfetcshx643vr3e

Architecture implications of pads as a scarce resource

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
In this paper, we develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation  ...  is and will remain a critical problem for architects and circuit designers alike.  ...  Acknowledgments This work is supported by NSF grant CNS-0916908 and MCDA-0903471, and DARPA MTO under contract no.HR0011-13-C-0022.  ... 
doi:10.1109/isca.2014.6853199 dblp:conf/isca/ZhangWMSS14 fatcat:yruivsyndbapvmp4izc3sbsc34

Low-Cost Protection for SER Upsets and Silicon Defects

Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd Austin
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
By utilizing low-cost techniques to address defects and SER, we keep protection costs significantly lower than traditional fault-tolerance approaches while providing high levels of coverage for a wide  ...  Our approach utilizes online built-in self-test (BIST) and microarchitectural checkpointing to detect, diagnose and recover the computation impaired by silicon defects or SER events.  ...  CONCLUSIONS In this paper we presented a low cost technology that protects a microprocessor pipeline and caches against transient faults caused by natural radiation-induced single-event upsets (SER) and  ... 
doi:10.1109/date.2007.364449 fatcat:3w6pm3mygzegjmgnjn54ijarwq

New Reprogrammable and Non-Volatile Radiation-Tolerant FPGA: RT ProASIC®3 [chapter]

Sana Rezgui
2010 Aerospace Technologies Advancements  
The Single Event Transients (SET) tolerance is hardened by single or duplication filtering [Shuler et al., 2005 & 2006 , Balasubramanian et al., 2005 , Baze et al., 2006 , Mavis & Eaton, 2007 , Rezgui  ...  If mitigation solutions of TMR and SET filtering are adopted for the logic and clock in A3P FPGA, the only remaining cross-section would be due to the transient event on the IO banks used for SE or LVDS  ...  Aerospace Technologies Advancements Edited by Thawar T. Arif How to reference In order to correctly reference this scholarly work, feel free to copy and paste the following: Sana Rezgui (2010) .  ... 
doi:10.5772/6936 fatcat:u6vk42qftrcolmbwrn4iz3u75m
« Previous Showing results 1 — 15 out of 1,810 results