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Reducing test time for 3D-ICs by improved utilization of test elevators
2014
2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)
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A highly efficient test compression scheme for 3D-ICs is proposed, which uses sequential linear decompressors local to each core. ...
This reduces test time and tester storage without any additional control. In addition, this architecture also minimizes the number of test elevators required to transfer the test data across layers. ...
This paper proposes a new architecture and methodology for test compression in core-based designs, which is better suited for 3D-ICs. ...
doi:10.1109/vlsi-soc.2014.7004157
dblp:conf/vlsi/MuthyalaT14
fatcat:trhk7hblvfen5gtwneyncrcdeu
Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs
[chapter]
2015
IFIP Advances in Information and Communication Technology
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Testing 3D-ICs poses additional challenges because of the need to transfer data to the non-bottom layers and the limited number of TSVs available in the 3D-ICs for the data transfer. ...
In addition, an inter-layer serialization technique is proposed, which further reduces the number of TSVs required, using simple hardware to serialize and deserialize the test data. ...
stack, to ensure the 3D-IC as a whole is not defective. ...
doi:10.1007/978-3-319-25279-7_2
fatcat:4t5isqsqtbh27bbz2lwpottmvm
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study
2013
2013 IEEE International Test Conference (ITC)
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For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multitower 3D DFT architecture is presented. ...
To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. ...
DFT architecture is controlled by the SOC-die level IEEE 1149.1 TAP controller. ...
doi:10.1109/test.2013.6651893
dblp:conf/itc/GoelAWCHMLCKVMSCLCK13
fatcat:ppi3xh7suzhdhfuhb6rce67jxi
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs
2016
2016 21th IEEE European Test Symposium (ETS)
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For stacked integrated circuits, effective test access requires the design-for-test (DfT) features in the various dies to operate in a concerted way to transport test stimuli and responses from and to ...
This paper presents a status report of P1838 and describes its three main hardware components: a serial control mechanism, a die wrapper register, and a flexible parallel port. ...
Acknowledgments The authors thank the other members of the IEEE Std P1838 Working Group for many fruitful discussions. ...
doi:10.1109/ets.2016.7519330
dblp:conf/ets/MarinissenMJ16
fatcat:iptknsczabfnnkmueecei4zyle
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
2011
Journal of electronic testing
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This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. ...
Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). ...
These so-called 3D Stacked ICs (3D-SICs) combine a smaller form factor and lower overall manufacturing costs [35] with many other compelling benefits, and hence their technology is quickly gaining ground ...
doi:10.1007/s10836-011-5269-9
fatcat:n4teyiysync6hfp3dovp2sv3mu
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers
2018
2018 IEEE 23rd European Test Symposium (ETS)
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IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. ...
For a realistic example FPP, we provide its formal specification. ...
We thank Patrick De Ryck of KU Leuven's Faculty of Engineering Technology for his supervision of the MSc graduation project of Yu Li and Ming Shao on the topic of this paper. ...
doi:10.1109/ets.2018.8400690
dblp:conf/ets/LiSJCBM18
fatcat:2xwllkarbzcshbpys7akwewurq
Test and debug solutions for 3D-stacked integrated circuits
2015
2015 IEEE International Test Conference (ITC)
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Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. ...
Testing has been identified as a showstopper for volume manufacturing of 3Dstacked integrated circuits (3D ICs). ...
This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. ...
doi:10.1109/test.2015.7342421
dblp:conf/itc/DeutschC15a
fatcat:nzulytvjz5dn3bgqnnqw6qx4oy
A hardware security solution against scan-based attacks
2016
2016 IEEE International Symposium on Circuits and Systems (ISCAS)
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TSV based 3D stacked ICs are expected to present significant performance improvements compared to the conventional 2D ICs. ...
A hardware security solution against sidechannel attacks and scan-based attacks for 3D ICs is a great research topic for future work. ...
doi:10.1109/iscas.2016.7538894
dblp:conf/iscas/MehtaSR16
fatcat:vyg6war4xfg57fjezfneaxj7nq
2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26
2018
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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., see 2723-2736
, VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957 ...
Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J ...
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. ...
doi:10.1109/tvlsi.2019.2892312
fatcat:rxiz5duc6jhdzjo4ybcxdajtbq
2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67
2020
IEEE Transactions on Circuits and Systems - II - Express Briefs
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, see Reda Mohamed, A., TCSII Sept. 2020 1529-1533 Qi, T., see Haider, M.F., TCSII Dec. 2020 3013-3017 Qi, W., Gao, M., Ahn, C.K., Cao, J., Cheng, J., and Zhang, L., Quantized Fuzzy Finite-Time Control ...
TCSII Sept. 2020 1539-1543 Jena, D., see Reddivari, R., TCSII Oct. 2020 2009-2013 Jeon, H., see Lee, D., TCSII Jan. 2020 67-71 Jeon, H., Bang, J., and Je, M., A CMRR Enhancement Circuit Employing Gₘ-Controllable ...
., +, TCSII Dec. 2020
3098-3102
Fault tolerance
A Cost-Aware Framework for Lifetime Reliability of TSV-Based 3D-IC
Design. ...
doi:10.1109/tcsii.2020.3047305
fatcat:ifjzekeyczfrbp5b7wrzandm7e
Three Dimensional Reconstruction
[chapter]
2014
Computer Vision
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TiKZ was used for diagrams. Content from our own publications Lobachev et al. [2013], Ulrich et al. [2014a] is allowed to be reproduced by the licensee. ...
We thank Norishige Fukushima for his implementation of SSIM. We used MI implementation written by Jose Delpiano. We thank anonymous reviewers for helpful comments that improved the presentation. ...
Andreas Kokott for the discussion of possible online banking improvements with the presented visualisation. ...
doi:10.1007/978-0-387-31439-6_100255
fatcat:mmnnsj55abennbinn3czg3n3oq
Fully-Integrated Heterogeneous DML Transmitters For High-Performance Computing
2019
Journal of Lightwave Technology
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This new computing architecture brings challenges and opportunities for novel optical interconnect solutions. ...
Thermal shunt and MOS capacitor structures were integrated into the lasers for effective thermal management and ultra low-energy tuning. It enables a ). A. ...
High-speed, low-latency, cost-and energy-effective optical interconnects play a pivotal role here to replace traditional copper counterparts for reach from tens of meters up to two kilometers in highperformance ...
doi:10.1109/jlt.2019.2959048
fatcat:l3zd3wibpvgytgl6ecpentyohe
Present State of CFD Softwares Application for Launch Vehicle Analysis
발사체 해석을 위한 CFD 소프트웨어 적용 현황
2020
Journal of the Korean Society of Propulsion Engineers
발사체 해석을 위한 CFD 소프트웨어 적용 현황
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Please visit the following URL for additional information: http://opensource .gsfc .nasa .gov/projects/xml2he/index . ...
an ISA100 . 11a stack . ...
Release Only Compressible Flow Toolbox LEW-17898-1 The Compressible Flow Toolbox is a set of algorithms that solve classical compressible equations for isentropic flow, fanno flow, Rayleigh flow, normal ...
doi:10.6108/kspe.2020.24.3.071
fatcat:trxkhiuqrjakll32bcjxskgwju
A high-throughput neurohistological pipeline for brain-wide mesoscale connectivity mapping of the common marmoset
2019
eLife
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Understanding the connectivity architecture of entire vertebrate brains is a fundamental but difficult task. ...
Here we present an integrated neuro-histological pipeline as well as a grid-based tracer injection strategy for systematic mesoscale connectivity mapping in the common Marmoset (Callithrix jacchus). ...
The data acquisition system is the central repository for image pre-processing 413 including image cropping, conversion, compression (Appendix 7). ...
doi:10.7554/elife.40042
pmid:30720427
pmcid:PMC6384052
fatcat:nd2ccovai5hy5bp276law5icsu
The visualization of hepatic vasculature by X-ray micro-computed tomography
2006
Journal of Electron Microscopy
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Ikuhara for useful discussions. This work was supported by the Kazato Research Foundation of Japan and JSPS KAKENHI Grant Numbers 17K14119 and 19H02606. ...
Part of this work was supported by the Research & Development Initiative for Scientific Innovation of New Generation Batteries 2 (RISING 2) project from the New Energy and Industrial Technology Development ...
For both image stacks, the specialist software Amira was used to reconstruct the ICMs in 3D. ...
doi:10.1093/jmicro/dfl015
pmid:16775217
fatcat:4udqurxlh5hjfjmq5nv6w2eroa
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