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IPDPS 2021 PhD Forum Welcome and Abstracts

2021 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)  
This year to help enhance the virtual presentations, in addition to the online availability of the posters, students were invited to include an abstract describing their work in the proceedings of the  ...  A compendium of these abstracts follows, noting that the posters will contain more detailed information including contact information of the authors.  ...  Based on the double-level execution model, the cost model of distributed DL helps to choose efficient HP strategies. Details of the cost model can be found in the poster and extended abstracts.  ... 
doi:10.1109/ipdpsw52791.2021.00160 fatcat:c5srphikvba6pklpxsyx6lfmhy

Lattice adaptive filter implementation for FPGA

Zdenek Pohl, Rudolf Matoušek, Jirí Kadlec, Milan Tichý, Miroslav Lícko
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
The poster briefly describes the important hardware issues involved with the FPGA based design of an evolutionary robot controller for the collision free navigation of mobile robots In code division multiple  ...  The employment of field programmable gate arrays (FPGAs) to a robot controller is very attractive, since it allows for fast IC prototyping and low cost modifications.  ...  Experimental results for a number of object tracking applications executed on resources embedded in cameras, show a significant amount of slack utilization FPGAs are being used in increasingly complex  ... 
doi:10.1145/611817.611877 dblp:conf/fpga/PohlMKTL03 fatcat:vg523unfzvcmvl2rsw4ja3ksma

FPGA-based design of an evolutionary controller for collision-free robot navigation

M. A. H. B. Azhar, K. R. Dimond
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
The poster briefly describes the important hardware issues involved with the FPGA based design of an evolutionary robot controller for the collision free navigation of mobile robots In code division multiple  ...  The employment of field programmable gate arrays (FPGAs) to a robot controller is very attractive, since it allows for fast IC prototyping and low cost modifications.  ...  Experimental results for a number of object tracking applications executed on resources embedded in cameras, show a significant amount of slack utilization FPGAs are being used in increasingly complex  ... 
doi:10.1145/611817.611852 dblp:conf/fpga/AzharD03 fatcat:juups7gn3ve2vhw2fbicwvt5kq

Subframe multiplexing for FPGA manufacturing test configuration

Erik Chmelar
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
The cost of FPGA manufacturing test is driven by the number of test configurations and the time required to configure an FPGA under test.  ...  The advantages of our method are the following: Application of a general constraint solver makes it possible to express many different sorts of constraints in a uniform manner.  ...  The poster deals with topological modelling of FPGA circuits for timing-driven algorithms.  ... 
doi:10.1145/968280.968315 dblp:conf/fpga/Chmelar04 fatcat:bkkwooxvszbvlfrg4b7h5svtvi

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

Vincenzo Conti, Leonardo Rundo, Giuseppe Billeci, Carmelo Militello, Salvatore Vitabile
2018 Energies  
In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources.  ...  Exploiting the ability of reconfiguring circuit portions at runtime, the latest generation of FPGAs can be used to foster a better balance between energy consumption and performance.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/en11040739 fatcat:evjp2d35krat3jjsmxqv4o2vj4

Microprocessor Optimizations for the Internet of Things: A Survey

Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The proliferation of these connected low-power devices will result in a data explosion that will significantly increase data transmission costs with respect to energy consumption and latency.  ...  While much research has focused on the IoT's connected nature and communication challenges, the challenges of IoT embedded computing with respect to device microprocessors has received much less attention  ...  , such as low cost, low energy budgets, and in some cases, real-time constraints.  ... 
doi:10.1109/tcad.2017.2717782 fatcat:nnf5vx3sd5dq3ic2qjexvi6euq

Dependable embedded systems

2008 2008 6th IEEE International Conference on Industrial Informatics  
Titles in the Series cover a focused set of embedded topics relating to traditional computing devices as well as hightech appliances used in newer, personal devices, and related topics.  ...  The material will vary by topic but in general most volumes will include fundamental material (when appropriate), methods, designs and techniques. More information about this series at  ...  It was a tremendous help to see to possibilities of FDSOI in silicon very early on.  ... 
doi:10.1109/indin.2008.4618103 fatcat:hal6brsgsjg5rlo3u5xil46pxi

Implementation of Fog computing for reliable E-health applications

Razvan Craciunescu, Albena Mihovska, Mihail Mihaylov, Sofoklis Kyriazakos, Ramjee Prasad, Simona Halunga
2015 2015 49th Asilomar Conference on Signals, Systems and Computers  
An important aspect is robust and resource efficient preamble design to minimize missed detection and false alarm probabilities of service requests.  ...  In addition, we will improve on the performance of such Coded ALOHA protocols in terms of the resource efficiency.  ...  Circuit area impacts energy dissipation per workload and chip cost.  ... 
doi:10.1109/acssc.2015.7421170 dblp:conf/acssc/CraciunescuMMKP15 fatcat:qm6mki5z6bcvrfimkmqjyrxaxm

Design of large polyphase filters in the Quadratic Residue Number System

Gian Carlo Cardarilli, Alberto Nannarelli, Yann Oster, Massimo Petricca, Marco Re
2010 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers  
The Riverside Optimizing Compiler for Configurable Circuits (ROCCC) is a C-to-VHDL compilation toolset designed to raise the abstraction of FPGA programming.  ...  FPXAs are abstract structures that can be targeted for implementation on applicationspecific integrated circuits, FPGAs, or other kinds of reconfigurable processors.  ... 
doi:10.1109/acssc.2010.5757589 fatcat:ccxnu5owr5fyrcjcqukumerueq

Ping-pong beam training for reciprocal channels with delay spread

Elisabeth de Carvalho, Jorgen Bach Andersen
2015 2015 49th Asilomar Conference on Signals, Systems and Computers  
In addition, we will improve on the performance of such Coded ALOHA protocols in terms of the resource efficiency.  ...  An important aspect is robust and resource efficient preamble design to minimize missed detection and false alarm probabilities of service requests.  ...  Circuit area impacts energy dissipation per workload and chip cost.  ... 
doi:10.1109/acssc.2015.7421451 dblp:conf/acssc/CarvalhoA15 fatcat:mqokuvnh3zg45licnfbgxyvxfu

Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs

Alexandra Kourfali, David Merodio Codinachs, Dirk Stroobandt
2017 2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)  
Predictive simulation applications to radiation hardened analog circuits design are discussed.  ...  Tomsk Polytechnic University, 6 National Research Nuclear University "MEPhI", 7 Novosibirsk State University Radiation hardened bandgap voltage reference was designed using Verilog-A physical modeling of  ...  for FPGA overlays, that provides fast run-time recovery from SEUs with minimal resources, via multiple layers of mitigation.POSTER AND RADIATION EFFECTS DATA WORKSHOP (REDW) SESSIONS 16:25-18:30 For more  ... 
doi:10.1109/radecs.2017.8696242 fatcat:frcrfuza2fdstitbsjoda5sn4y

Program

2020 2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)  
To this end, we propose optimizing the thermostat set-points of the EWHs in residential houses with the objective of minimizing the energy cost associated with the residential houses having PEVs.  ...  The FPGA resource utilization increased but it was well under 5% of the total resources available on the FPGA chip, achieving a speed up of 2x when compared to the RTL-based design for the RADAR system  ...  the effectiveness of the proposed forecasting module in minimizing the DC cost of the class-A electricity customer.  ... 
doi:10.1109/ccece47787.2020.9255763 fatcat:mpf7smikpfc77bu73ciqstdagm

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
2020 IEEE Access  
In a scenario where several sophisticated algorithms need to be executed with limited energy and low latency, the need for cost-effective hardware platforms capable of implementing energy-efficient DL  ...  This work summarizes and compares the works for four leading platforms for the execution of algorithms such as CPU, GPU, FPGA and ASIC describing the main solutions of the state-of-the-art, giving much  ...  of the computational resources, of the on-chip buffers and of the schedule RomaNet [144] 2019 Minimize off-chip memory accesses MEM Given a NN layer, optimization of tiling and partitioning MAESTRO  ... 
doi:10.1109/access.2020.3039858 fatcat:nticzqgrznftrcji4krhyjxudu

Harnessing Adaptivity Analysis for the Automatic Design of Efficient Embedded and HPC Systems

Silvia Lovergine, Fabrizio Ferrandi
2013 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum  
in area and complexity of the circuit, or take a conservative approach, with consequent decrease in performance.  ...  Given the different scale of the problem in the ESs and HPCs domain, Adaptivity Analysis is defined at two distinct abstraction levels.  ...  Such algorithm attempts to minimize the resources required to meet a specified global time constraint.  ... 
doi:10.1109/ipdpsw.2013.230 dblp:conf/ipps/LovergineF13 fatcat:vpdgybp2gnbmve6wzgscv6hqoa

Computational Cell Biology

J. Sneyd
2003 Mathematical Medicine and Biology  
We also present the first algorithm that computes, in such a general framework, every rule that satisfies both a minimal frequency constraint and minimal confidence constraints.  ...  as an FPGA implementation [43] .  ... 
doi:10.1093/imammb20.1.131 fatcat:6sml7goilrdvjphvvhsuerpyuy
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