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3D-ICE 3.0: efficient nonlinear MPSoC thermal simulation with pluggable heat sink models

Federico Terraneo, Alberto Leva, William Fornaciari, Marina Zapater, David Atienza
2021 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The increasing power density in modern highperformance multi-processor system-on-chip (MPSoC) is fueling a revolution in thermal management.  ...  Support for nonlinear dynamic models is included, for instance to accurately represent variable coolant flows.  ...  tures, to perform thermal-aware MPSoC design and evaluate thermal control policies [12] , [13] .  ... 
doi:10.1109/tcad.2021.3074613 fatcat:fm6p7hom2nejjdh4r4t3xcks3m

An SMDP-Based Approach to Thermal-Aware Task Scheduling in NoC-based MPSoC platforms [article]

Farnaz Niknia, Kiamehr Rezaee, Vesal Hakami
2020 arXiv   pre-print
In this paper, we consider the operation of a thermal-aware task scheduler, dispatching tasks from an arrival queue as well as setting the voltage and frequency of the processing cores to optimize the  ...  mean temperature margin of the entire chip (i.e., cores as well as the NoC routers).  ...  The work presented in [24] proposes a temperature-aware task scheduling approach for streaming applications on mesh-based NoC systems.  ... 
arXiv:2009.02813v1 fatcat:puuf6nkvzrhsdpj65qz2f6xa2u

Safepower Project: Architecture For Safe And Power-Efficient Mixed-Criticality Systems

Maher Fakih, Alina Lenz, Mikel Azkarate-Askasua, Javier Coronel, Alfons Crespo, Simon Davidmann, Juan Carlos Diaz Garcia, Nera González Romero, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Roman Obermaisser (+6 others)
2017 Zenodo  
With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip.  ...  different granularity levels running on an FPGA-based MPSoC.  ...  The second one performs thermal management. It primarily relies on the placement of threads in cores to avoid thermal hotspots and temperature gradients. At last, asymmetric systems are depicted.  ... 
doi:10.5281/zenodo.1216870 fatcat:46gbqu45lzct5mhsspuqt5i4wm

2019 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 38

2019 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., +, TCAD Dec. 2019 2201-2214 Filtering theory Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC.  ...  ., +, TCAD April 2019 755-766 A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap Flash Memory.  ... 
doi:10.1109/tcad.2020.2964359 fatcat:qjr6i73tkrgnrkkmtjexbxberm

Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip [chapter]

Liang Wang, Xiaohang Wang, Terrence Mak
2015 IFIP Advances in Information and Communication Technology  
A dynamic programming-based lifetime-aware routing algorithm is proposed to optimize the lifetime distribution of routers.  ...  A metric lifetime budget is associated with each router, indicating the maximum allowed workload for current period.  ...  Experimental Results Experimental Setup Experiments are performed using Noxim simulator, which is an open source Sys-temC simulator for mesh-based NoC.  ... 
doi:10.1007/978-3-319-25279-7_1 fatcat:yorysmmzifavdcjcaoowaaocey

2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39

2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., +, TCAD Dec. 2020 4635-4644 Thermal management (packaging) Augmented Cross-Entropy-Based Joint Temperature Optimization of Real-Time 3-D MPSoC Systems. 1987 -1999 Sept. 1925 Sept. -1934 .,  ...  Wu, B., +, TCAD April 2020 803-815 Temperature sensors A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.  ...  Entropy-Directed Scheduling for FPGA High-Level Synthesis. Shen, M., +, TCAD Oct. 2020 2588 -2601 FLASH: Fast, Parallel, and Accurate Simulator for HLS.  ... 
doi:10.1109/tcad.2021.3054536 fatcat:wsw3olpxzbeclenhex3f73qlw4

Dynamic power management for multidomain system-on-chip platforms

Paul Bogdan, Radu Marculescu, Siddharth Jain
2013 ACM Transactions on Design Automation of Electronic Systems  
, such characteristics lead to inefficient communication and resources allocation, as well as high power dissipation in MPSoCs.  ...  Reducing energy consumption in multiprocessor systems-on-chip (MPSoCs) where communication happens via the network-on-chip (NoC) approach calls for multiple voltage/frequency island (VFI)-based designs  ...  ACKNOWLEDGMENTS The authors thank the anonymous reviewers for their valuable comments and suggestions to improve our manuscript.  ... 
doi:10.1145/2504904 fatcat:mwt37atpzjbxlg4fjbnn5pwfkm

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach

Amir-Mohammad Rahmani, Mohammad-Hashem Haghbayan, Anil Kanduri, Awet Yemane Weldezion, Pasi Liljeberg, Juha Plosila, Axel Jantsch, Hannu Tenhunen
2015 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)  
Power management of NoC-based manycore systems with runtime application mapping becomes more challenging in the dark silicon era.  ...  Acknowledgment The authors acknowledge the financial support by the Academy of Finland project entitled "MANAGE: Data Management of 3D Systems for the Dark Silicon Age" and EU COST Actions IC1103: Manufacturable  ...  This work is not dark silicon aware either, as they do not utilise feedback from power sensors to avoid violating the TSP/TDP. Haghbayan et al.  ... 
doi:10.1109/islped.2015.7273517 dblp:conf/islped/RahmaniHKWLPJT15 fatcat:prhqji4kybfnzpwsjmn7asgy2m

Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software

Abbas Rahimi, Luca Benini, Rajesh K. Gupta
2016 Proceedings of the IEEE  
We conclude with an outlook for the emerging field.  ...  We provide a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software.  ...  On-Chip Sensors: Foxton technology utilizes on-chip thermal sensors in conjunction with ADC to measure power and temperature of an Itanium family processor [153] .  ... 
doi:10.1109/jproc.2016.2518864 fatcat:sxrsu3excbdg5p7sk4iczz262y

Exploring manycore architectures for next-generation HPC systems through the MANGO approach

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragić, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella (+22 others)
2018 Microprocessors and microsystems  
thermal-aware resource allocation and management of these applications when running on MPSoCs.  ...  Temperature sensors are usually available as an average for the whole CPU.  ... 
doi:10.1016/j.micpro.2018.05.011 fatcat:gf4jczkxgzcpfdbgqygmwbkwfq

DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework [article]

Samet E. Arda, Anish NK, A. Alper Goksoy, Nirmal Kumbhare, Joshua Mack, Anderson L. Sartor, Ali Akoglu, Radu Marculescu, Umit Y. Ogras
2020 arXiv   pre-print
To this end, system-level design - including scheduling, power-thermal management algorithms and design space exploration studies - plays a crucial role.  ...  However, this potential is contingent upon optimizing the SoC for the target domain and utilizing its resources effectively at runtime.  ...  Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon.  ... 
arXiv:2003.09016v1 fatcat:mnupp3onafd6tcerxukln7hgtm

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Prateek Shantharama, Akhilesh S. Thyagaturu, Martin Reisslein
2020 IEEE Access  
The goal of the optimization is to allocate tasks across Multi-Processor SoC (MPSoC) for maximizing the resource utilization and minimizing the processing latency of each task.  ...  The 2D mesh technology implements a mesh based interconnect to connect all the cores on a given die, i.e., single CPU socket.  ... 
doi:10.1109/access.2020.3008250 fatcat:kv4znpypqbatfk2m3lpzvzb2nu

An Outlook on Design Technologies for Future Integrated Systems

G. De Micheli
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper surveys design requirements and solutions for heterogeneous systems and addresses design technologies for realizing them.  ...  The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is  ...  , thus effecting temperature-aware load balancing [89] (Fig. 4) .  ... 
doi:10.1109/tcad.2009.2021008 fatcat:2qujxzmnjbfebd4fg3bnrzsjua


Presentata Da, Mohammadsadegh, Sadri Coordinatore, Dottorato Relatore, Vanelli Alessandro, Coralli, Luca Benini, Mohammadsadegh Sadri
Furthermore, we extend the temperature variation aware analysis of designs to 3D MPSoCs with Wide-I/O DRAM.  ...  We also develop an infrastructure for online monitoring of SCC temperature sensor readings and SCC power consumption. We create a power and a thermal model for Intel SCC.  ...  Based on the results it creates a multi-granularity mesh which is used for thermal simulation.  ... 

Power-Aware and Temperature-Aware Design Automation

Zhenyu Gu
2007 unpublished
Power-Aware and Temperature-Aware Design Automation Zhenyu Gu This dissertation presents several topics which are related to temperature-aware and poweraware design.  ...  Chapter 3 presented a temperature-aware high-level synthesis algorithm built upon the framework of Chapter 2.  ...  Power-Aware and Temperature-Aware Design Flow In this section, we explain the challenges for preventing thermal problems based on our proposed temperature-aware synthesis design flow.  ... 
doi:10.21985/n25727 fatcat:xixmg67iubfonimpzi7erfbc4m
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