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Correctness of Hierarchical MCS Locks with Timeout [article]

Milind Chabbi, Abdelhalim Amer, Shasha Wen, Xu Liu
2016 arXiv   pre-print
This manuscript serves as a correctness proof of the Hierarchical MCS locks with Timeout (HMCS-T) described in our paper titled "An Efficient Abortable-locking Protocol for Multi-level NUMA Systems" appearing  ...  We model check these configurations, which proves the correctness of components of an HMCS-T lock. Finally, building upon these facts, we argue logically for the correctness of HMCS-T.  ...  {swen, xl10}@cs.wm.edu This manuscript serves as a correctness proof of the Hierarchical MCS locks with Timeout (HMCS-T) described in our paper [1] titled "An Efficient Abortable-locking Protocol for  ... 
arXiv:1612.09576v1 fatcat:qff4lvqmk5fvlkklktevy7rfya

An Efficient Abortable-locking Protocol for Multi-level NUMA Systems

Milind Chabbi, Abdelhalim Amer, Shasha Wen, Xu Liu
2017 SIGPLAN notices  
In this paper, we design and evaluate the HMCS-T lock, a Hierarchical MCS (HMCS) lock variant that admits a timeout.  ...  Enhancing locality-aware locks with lightweight timeout capability is critical for their adoption.  ...  However, stateof-the-art hierarchical queue-based locks (e.g., [5] ) lack the timeout capability. Few, if any, verify their correctness.  ... 
doi:10.1145/3155284.3018768 fatcat:mow7mm4ztfaxnfstxm5suonwna

An Efficient Abortable-locking Protocol for Multi-level NUMA Systems

Milind Chabbi, Abdelhalim Amer, Shasha Wen, Xu Liu
2017 Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming - PPoPP '17  
In this paper, we design and evaluate the HMCS-T lock, a Hierarchical MCS (HMCS) lock variant that admits a timeout.  ...  Enhancing locality-aware locks with lightweight timeout capability is critical for their adoption.  ...  However, stateof-the-art hierarchical queue-based locks (e.g., [5] ) lack the timeout capability. Few, if any, verify their correctness.  ... 
doi:10.1145/3018743.3018768 fatcat:hldqj7uw3zcjxnelky7n5nmqui

Compact NUMA-Aware Locks [article]

Dave Dice, Alex Kogan
2019 arXiv   pre-print
Virtually all those locks, however, are hierarchical in their nature, thus requiring space proportional to the number of sockets.  ...  Unlike MCS, the new lock organizes waiting threads in two queues, one composed of threads running on the same socket as the current lock holder, and another composed of threads running on a different socket  ...  They present HMCS, a hierarchical MCS lock, in which each level of the hierarchy is protected by an MCS lock.  ... 
arXiv:1810.05600v2 fatcat:sdjwfpninjexjkv37xwo3n27zm

NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures [article]

Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan
2020 arXiv   pre-print
By training NN on conjunctive normal forms (CNFs) corresponded to a dataset of logic locked circuits, as well as fine-tuning the confidence rate of the NN prediction, our experiments show that NNgSAT could  ...  solve 93.5% of the logic locked circuits containing complex structures within a reasonable time, while the existing SAT attack cannot proceed the attack flow in them.  ...  When there exists no more DIP, it returns UNSAT, revealing the correct key with one more SAT solving. guesses SAT on an UNSAT problem.  ... 
arXiv:2009.02208v1 fatcat:zcutojedxnc6zbwsnurhayp44q

Lock cohorting

David Dice, Virendra J. Marathe, Nir Shavit
2012 Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming - PPoPP '12  
Our new cohorting technique allows us to easily create NUMA-aware versions of the TATAS-Backoff, CLH, MCS, and ticket locks, to name a few.  ...  We empirically compared the performance of cohort locks with prior NUMA-aware and classic NUMA-oblivious locks on a synthetic micro-benchmark, a real world key-value store application memcached, as well  ...  ] ) locks and the last two are abortable (timeout capable) locks.  ... 
doi:10.1145/2145816.2145848 dblp:conf/ppopp/DiceMS12 fatcat:o62jiu67kngrni4smmnxamjvzq

Lock Cohorting

David Dice, Virendra J. Marathe, Nir Shavit
2015 ACM Transactions on Parallel Computing  
Our new cohorting technique allows us to easily create NUMA-aware versions of the TATAS-Backoff, CLH, MCS, and ticket locks, to name a few.  ...  We empirically compared the performance of cohort locks with prior NUMA-aware and classic NUMA-oblivious locks on a synthetic micro-benchmark, a real world key-value store application memcached, as well  ...  ] ) locks and the last two are abortable (timeout capable) locks.  ... 
doi:10.1145/2686884 fatcat:o4fbwxw6ufbndlmtv66cam2izq

Lock cohorting

David Dice, Virendra J. Marathe, Nir Shavit
2012 SIGPLAN notices  
Our new cohorting technique allows us to easily create NUMA-aware versions of the TATAS-Backoff, CLH, MCS, and ticket locks, to name a few.  ...  We empirically compared the performance of cohort locks with prior NUMA-aware and classic NUMA-oblivious locks on a synthetic micro-benchmark, a real world key-value store application memcached, as well  ...  ] ) locks and the last two are abortable (timeout capable) locks.  ... 
doi:10.1145/2370036.2145848 fatcat:4u65zq73f5f75m6ysva72i66f4

Architectural Support for Fair Reader-Writer Locking

Enrique Vallejo, Ramon Beivide, Adrian Cristal, Tim Harris, Fernando Vallejo, Osman Unsal, Mateo Valero
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
By associating a unique thread-id to each lock request we decouple the hardware lock from the requestor core. This provides correct and efficient execution in the presence of thread migration.  ...  to be associated with every memory location, rely on the low latencies of single-chip multicore designs or are slow in adversarial cases such as suspended threads in a lock queue.  ...  This work is supported by the cooperation agreement between the Barcelona Supercomputing Center -National Supercomputer Facility and Microsoft Research, by the Ministry of Science and Technology of Spain  ... 
doi:10.1109/micro.2010.12 dblp:conf/micro/VallejoBCHVUV10 fatcat:hftntmhjrfdtdbywsgvgr5ixfa

A new model for context-aware transactions in mobile services

Muhammad Younas, Soraya Kouadri Mostéfaoui
2011 Personal and Ubiquitous Computing  
With the ubiquity of handheld devices (such as smart phones and PDAs) and the availability of a wide range of mobile services (such as mobile banking, road traffic updates, and weather forecast) people  ...  This paper designs and develops the proposed transaction model and evaluates its performance in terms of time and message complexities as well as transaction's throughput.  ...  locking) thus retaining control of their resources.  ... 
doi:10.1007/s00779-011-0369-1 fatcat:ow75za2w4vhwpfm6tikk7abkoy

It's Time: OS Mechanisms for Enforcing Asymmetric Temporal Integrity [article]

Anna Lyons, Gernot Heiser
2016 arXiv   pre-print
They must guarantee deadlines of highly-critical tasks at the expense of lower-criticality ones in the case of overload.  ...  Mixed-criticality systems combine real-time components of different levels of criticality, i.e. severity of failure, on the same processor, in order to obtain good resource utilisation.  ...  seL4 seL4 is a high-performance OS microkernel with an unprecedented degree of assurance: it features formal proofs of implementation correctness down to the binary, proofs of spatial isolation properties  ... 
arXiv:1606.00111v2 fatcat:snps4qljjzddnfnkv52x5tzyl4

Efficient verification of periodic programs using sequential consistency and snapshots

Sagar Chaki, Arie Gurfinkel, Nishant Sinha
2014 2014 Formal Methods in Computer-Aided Design (FMCAD)  
Our approach is able to handle periodic programs that synchronize via two commonly used types of locks -priority ceiling protocol (PCP) locks, and CPU locks.  ...  We develop an approach based on generating, and solving, a provably correct verification condition (VC).  ...  Our solution is based on the BMC-MC paradigm and consists of two steps: (i) generate a provably correct VC; (ii) solve the VC using a SMT engine.  ... 
doi:10.1109/fmcad.2014.6987595 dblp:conf/fmcad/ChakiGS14 fatcat:3xjfmzn4i5grpfsbo6ad5l7zam

Self-Aware Scheduling for Mixed-Criticality Component-Based Systems

Johannes Schlatow, Mischa Mostl, Rolf Ernst
2019 2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)  
We provide a novel approach to this challenge by applying self-aware computing methodologies that involve runtime monitoring to detect (and correct) model deviations of a budget-based scheduler.  ...  Correct models are, however, a prerequisite when response times are bounded by formal analyses.  ...  ACKNOWLEDGEMENT This work was funded as part of the DFG Research Unit Controlling Concurrent Change, funding number FOR 1800.  ... 
doi:10.1109/rtas.2019.00030 dblp:conf/rtas/SchlatowME19 fatcat:bpjjzui7nvcshjsuvf5tv64tcq

VM-based shared memory on low-latency, remote-memory-access networks

Leonidas Kontothanassis, Galen Hunt, Robert Stets, Nikolaos Hardavellas, Michał Cierniak, Srinivasan Parthasarathy, Wagner Meira, Sandhya Dwarkadas, Michael Scott
1997 Proceedings of the 24th annual international symposium on Computer architecture - ISCA '97  
Recent technological advances have produced network interfaces that provide users with very low-latency ac- cess to the memory of remote machines.  ...  In our experiments, Cashmere scales slightly better than TreadMarks for applications with fine-grain interleaving of accesses to shared data.  ...  In addition to using dirty bits, we plan to experiment with hierarchical locking for directories [37] and with alternatives to write-doubling based on twins and diffs or on software dirty bits [33]  ... 
doi:10.1145/264107.264163 dblp:conf/isca/KontothanassisHSHCPMDS97 fatcat:l7qdbzcwanebpe5jbmvyv2lo6a

VM-based shared memory on low-latency, remote-memory-access networks

Leonidas Kontothanassis, Galen Hunt, Robert Stets, Nikolaos Hardavellas, Michał Cierniak, Srinivasan Parthasarathy, Wagner Meira, Sandhya Dwarkadas, Michael Scott
1997 SIGARCH Computer Architecture News  
Recent technological advances have produced network interfaces that provide users with very low-latency ac- cess to the memory of remote machines.  ...  In our experiments, Cashmere scales slightly better than TreadMarks for applications with fine-grain interleaving of accesses to shared data.  ...  In addition to using dirty bits, we plan to experiment with hierarchical locking for directories [37] and with alternatives to write-doubling based on twins and diffs or on software dirty bits [33]  ... 
doi:10.1145/384286.264163 fatcat:q4cglf5nyzdajpeilyandf46ni
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