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Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Jose Nunez-Yanez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Dario Suarez, Ruben Gran
2018 Journal of Supercomputing  
General rights This document is made available in accordance with publisher policies. Please cite only the published version using the reference above.  ...  Table 2 2 Energy change when the second CPU core is utilised provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate  ...  distributed under the terms of the Creative Commons Attribution 4.0 Interna- tional License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in  ... 
doi:10.1007/s11227-018-2409-3 fatcat:ig4eiv4gmjeizira2mb3xqvaeq

Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Jose Nunez-Yanez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Dario Suarez, Ruben Gran
2018 Journal of Supercomputing  
In this paper, we investigate how to enhance an existing software-defined framework B Sam Amiri J.  ...  For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only  ...  any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.  ... 
doi:10.1007/s11227-018-2367-9 fatcat:gyiyxrbvcnbchcsr4ar6bxirwq

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$ [chapter]

Haris Isakovic, Radu Grosu, Denise Ratasich, Jiri Kadlec, Zdenek Pohl, Steve Kerrison, Kyriakos Georgiou, Kerstin Eder, Norbert Druml, Lillian Tadros, Flemming Christensen, Emilie Wheatley (+3 others)
2017 Lecture Notes in Computer Science  
In the sandbox world of cyber-physical systems and internetof-things a number of applications is only eclipsed by a number of products that provide solutions for specific problem or set of problems.  ...  It also provides a short overview of several technologies explored in the project that provide bridging solutions for these problems.  ...  Acknowledgment This research has received funding from the ARTEMIS Joint Undertaking (JU) in european project EM C 2 under grant agreement n • 621429.  ... 
doi:10.1007/978-3-319-66284-8_12 fatcat:6u7actbbcbgwna37sit2rcuhqq

Utilizing Hierarchical Multiprocessing for Medical Image Registration

William Plishker, Omkar Dandekar, Shuvra Bhattacharyya, Raj Shekhar
2010 IEEE Signal Processing Magazine  
, but there has yet to be a solution fast enough and effective enough to gain widespread clinical use.  ...  One way to tap into the potential of this raw data is to merge these images into one integrated view through a procedure called image registration.  ...  His application areas of interest include medical imaging, software defined radio, networking, and high energy physics.  ... 
doi:10.1109/msp.2009.935419 fatcat:3j63mqfj7za27engn2pokpcwgq

Benefits of Cyber-Physical Systems Modeling and Simulation with LabView

Csaba Szász
2021 Recent Innovations in Mechatronics  
Both advantages and shortcomings of this very special technology are studied in order to design and implement a viable software framework being able to model and simulate various CPS structures.  ...  In the past years a huge number of research papers has been dedicated to identify and develop modeling techniques and simulation toolkits being able to handle CPSs complexity.  ...  Obviously, in order to advance in this topic a well-defined multidisciplinary approach is required.  ... 
doi:10.17667/riim.2021.1/3. fatcat:6k55yyflyrfhlnsjkxxbqjxxc4

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment

Mateus B. Rutzig, Antonio C. S. Beck, Felipe Madruga, Marco A. Alves, Henrique C. Freitas, Nicolas Maillard, Philippe O. A. Navaux, Luigi Carro
2011 International Journal of Reconfigurable Computing  
Therefore, in this work, we have expanded the DIM (dynamic instruction merging) technique to be used in a multiprocessing scenario, proving the need for an adaptable ILP exploitation even in TLP architectures  ...  Current multiprocessing systems are composed either of many homogeneous and simple cores or of complex superscalar, simultaneous multithread processing elements.  ...  Reconfigurable Multiprocessing System Section 3 demonstrated that in a heterogeneous application environment, TLP and ILP exploitation are complementary.  ... 
doi:10.1155/2011/546962 fatcat:rxidkhq36vgdthe4jvqvsrtq6y

Logic partition orderings for multi-FPGA systems

Scott Hauck, Gaetano Borriello
1995 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays - FPGA '95  
., determining the way in which a circuit should be bipartitioned so as to best map it to a multi-FPGA system. This allows multi-FPGA partitioners to harness standard partitioning techniques.  ...  One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning.  ...  Acknowledgments This research was funded in part by the Advanced Research Projects Agency under Contract N00014-J-91-4041. Scott Hauck was supported by an AT&T Fellowship.  ... 
doi:10.1145/201310.201315 dblp:conf/fpga/HauckB95 fatcat:jvxlun3tazgtvjstrykdvbh5se

Logic Partition Orderings for Multi-FPGA Systems

S. Hauck, G. Borriello
1995 Third International ACM Symposium on Field-Programmable Gate Arrays  
., determining the way in which a circuit should be bipartitioned so as to best map it to a multi-FPGA system. This allows multi-FPGA partitioners to harness standard partitioning techniques.  ...  One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning.  ...  Acknowledgments This research was funded in part by the Advanced Research Projects Agency under Contract N00014-J-91-4041. Scott Hauck was supported by an AT&T Fellowship.  ... 
doi:10.1109/fpga.1995.241942 fatcat:vd2d4hilargahmqtffjymcliie

Design of a Low-Power Embedded System Based on a SoC-FPGA and the Honeybee Search Algorithm for Real-Time Video Tracking

Carlos Soubervielle-Montalvo, Oscar E. Perez-Cham, Cesar Puente, Emilio J. Gonzalez-Galvan, Gustavo Olague, Carlos A. Aguirre-Salado, Juan C. Cuevas-Tello, Luis J. Ontanon-Garcia
2022 Sensors  
A general recommendation obtained from this research is to use SoC-FPGA over CPU-GPU to work with meta-heuristics in computer vision applications when an embedded solution is required.  ...  Our findings demonstrated that the combination of SoC-FPGA and HSA reduced the consumption of computational resources, allowing real-time multiprocessing without a reduction in precision, and with the  ...  In embedded system design, it is very important to focus efforts on a well-defined specific application.  ... 
doi:10.3390/s22031280 pmid:35162025 pmcid:PMC8840388 fatcat:fv3iziahqbg35py5wliatrc67m

Towards a Java multiprocessor

Christof Pitter, Martin Schoeberl
2007 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems - JTRES '07  
Finally yet importantly, the first implementation of the CMP composed of two/three JOPs in an FPGA enables us to present a comparison of the performance between a single-core JOP and the CMP version by  ...  A major challenge in CMP is the shared memory access of multiple CPUs.  ...  The two leaders of the FPGA market Altera and Xilinx both provide software tools and intellectual property (IP) processors to design CMP systems [2, 5] .  ... 
doi:10.1145/1288940.1288962 dblp:conf/jtres/PitterS07 fatcat:kymjieugtfg4va4l375ek256ue

dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs [chapter]

Paul Grigoras, Pavel Burovskiy, James Arram, Xinyu Niu, Kit Cheung, Junyi Xie, Wayne Luk
2017 Lecture Notes in Computer Science  
We propose an approach for performance critical applications including standard library modules, benchmarking facilities and application benchmarks to support a variety of use-cases.  ...  However the limited development productivity has prevented mainstream adoption of FPGAs in many areas such as High Performance Computing.  ...  ranging from timing utilities to APIs for reordering sparse matrix data in preparation for FPGA execution; 2) tools for creating and managing projects such as to compile, generate and manage multiprocess  ... 
doi:10.1007/978-3-319-56258-2_26 fatcat:7yf4ugpekvamdnrnphxlti2sm4

Model-Based Firmware Generation for Acquisition Systems Using Heterogeneous Hardware

Rens Baeyens, Joachim Denil, Jan Steckel, Walter Daems
2022 Automation  
In this work, a model-based code generator is developed to abstract the user from the actual software implementation.  ...  Therefore, a model-based approach on control and signal processing systems using affordable heterogeneous hardware is proposed.  ...  The latter combination currently exists in the form of field programmable gate arrays (FPGAs) with soft-core CPUs, e.g., a Xilinx Spartan 6 FPGA combined with a MicroBlaze soft CPU, as an FPGA SoC using  ... 
doi:10.3390/automation3030024 fatcat:ka3lwijeo5cznjqexxkg3hcamm

State-of-the-art in Heterogeneous Computing

Andre R. Brodtkorb, Christopher Dyken, Trond R. Hagen, Jon M. Hjelmervik, Olaf O. Storaasli
2010 Scientific Programming  
We present a review of hardware, available software tools, and an overview of state-of-the-art techniques and algorithms.  ...  programmable gate arrays (FPGAs).  ...  ACKNOWLEDGEMENTS The authors would like to thank Gernot Ziegler at NVIDIA Corporation, Knut-Andreas Lie and Johan Seland at SINTEF ICT, and Praveen Bhaniramka and Gaurav Garg at Visualization Experts Limited  ... 
doi:10.1155/2010/540159 fatcat:xu4n5ubgfzh3bobd445cmg7qyu

Direct N-body code on low-power embedded ARM GPUs [article]

David Goz, Sara Bertocco, Luca Tornatore, Giuliano Taffoni
2019 arXiv   pre-print
A state-of-the-art direct N-body code suitable for astrophysical simulations has been re-engineered in order to exploit SoC heterogeneous platforms based on ARM CPUs and embedded GPUs.  ...  SoC boards are heterogeneous architecture where computing power is supplied both by CPUs and GPUs, and are emerging as a possible low-power and low-cost alternative to clusters based on traditional CPUs  ...  threshold), CPU migration (pairing every big core with a LITTLE core), and heterogeneous multiprocessing mode (also known as Global Task Scheduling, which allows using all of the cores simultaneously)  ... 
arXiv:1901.08532v1 fatcat:qrws2v2ppjecboupymbvesoj2q

An Outlook on Design Technologies for Future Integrated Systems

G. De Micheli
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
paving the way to a new class of heterogeneous integrated systems, with increased performance and connectedness and providing us with gateways to the living world.  ...  The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is  ...  Moreover, software applications and operating systems need to be rethought for multiprocessing platforms, and thus multiprocessing does not deliver yet the expected gain on standard applications.  ... 
doi:10.1109/tcad.2009.2021008 fatcat:2qujxzmnjbfebd4fg3bnrzsjua
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