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Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, N. Vijaykrishnan, Chita R. Das
2011 Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11  
Our scheme is based on the observation that instead of staggering requests to a write-busy STT-RAM bank, the network should schedule requests to other idle cache banks for effectively hiding the latency  ...  In this paper, we study the integration of STT-RAM in a 3D multi-core environment and propose solutions at the on-chip network level to circumvent the write overhead problem in cache architecture with  ...  ACKNOWLEDGEMENTS We would like to thank the anonymous reviewers for their reviews and comments in improving this paper.  ... 
doi:10.1145/2000064.2000074 dblp:conf/isca/MishraDSXVD11 fatcat:pg6o6cr655dsbkwab7hv7y3qda

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, N. Vijaykrishnan, Chita R. Das
2011 SIGARCH Computer Architecture News  
Our scheme is based on the observation that instead of staggering requests to a write-busy STT-RAM bank, the network should schedule requests to other idle cache banks for effectively hiding the latency  ...  In this paper, we study the integration of STT-RAM in a 3D multi-core environment and propose solutions at the on-chip network level to circumvent the write overhead problem in cache architecture with  ...  ACKNOWLEDGEMENTS We would like to thank the anonymous reviewers for their reviews and comments in improving this paper.  ... 
doi:10.1145/2024723.2000074 fatcat:7pyftbeswfgldp4f7wbbrvo4f4

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Jeren Samandari-Rad, Richard Hughey
2016 IEEE Access  
In this paper, we extend our previously proposed hybrid analyticalempirical model for minimizing and predicting the delay and delay variability of SRAMs, VAR-TX, to a new enhanced version, exVAR-TX, to  ...  Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs.  ...  Spin-transfer torque random access memory (STT-RAM) have the potential to facilitate or even resolve some of the major challenging issues discussed in this paper.  ... 
doi:10.1109/access.2016.2521385 fatcat:vowwzjai7jhg3iezcclnpdph3e

Special Session: Reliability Analysis for ML/AI Hardware [article]

Shamik Kundu, Kanad Basu, Mehdi Sadi, Twisha Titirsha, Shihao Song, Anup Das, Ujjwal Guin
2021 arXiv   pre-print
Finally, we present two key reliability issues -- circuit aging and endurance in emerging neuromorphic hardware platforms and present our system-level approach to mitigate them.  ...  The first section outlines the reliability issues in a commercial systolic array-based ML accelerator in the presence of faults engendering from device-level non-idealities in the DRAM.  ...  Reliability Issues NVMs High-voltage related circuit aging PCM, Flash High-current related circuit aging OxRAM, STT-MRAM Read disturbance All Limited endurance All to implement synaptic storage  ... 
arXiv:2103.12166v2 fatcat:eceha3a6ibgojeokkg5gm3zywq

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities

Weiqiang Liu, Chongyan Gu, Maire O'Neill, Gang Qu, Paolo Montuschi, Fabrizio Lombardi
2020 Proceedings of the IEEE  
It shows that STT-RAM achieved comparable performance compared to DRAM and is a very promising memory technology.  ...  A comprehensive evaluation of using STT-RAM to replace DRAM technology is investigated in [111] .  ... 
doi:10.1109/jproc.2020.3030121 fatcat:vgxrxqkoibhgflrwq6rrfz7ofm

Trends on the application of emerging nonvolatile memory to processors and programmable devices

Lionel Torres, Raphael Martins Brum, Luis Vitorio Cargnini, Gilles Sassatelli
2013 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)  
M.; Guillemenet, Y.; Sassatelli, G., "Embedded MRAM for high-speed computing," VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/I-  ...  ., "Trends on the application of emerging nonvolatile memory to processors and programmable devices," Circuits and Sys-Torres, L.; Brum, R.M.; Guillemenet, Y.; Sassatelli, G.; Cargnini, L.V., "Evaluation  ...  A L1 CACHE built with ultra low retention STT-MRAM coupled with the proposed dynamic refresh scheme can achieve 9.2% in performance improvement, and saves up to 30% of the total energy, when compared to  ... 
doi:10.1109/iscas.2013.6571792 dblp:conf/iscas/TorresBCS13 fatcat:aommoaizybhufp76nxuappbxby

Eurolab-4-HPC Long-Term Vision on High-Performance Computing [article]

Theo Ungerer, Paul Carpenter
2018 arXiv   pre-print
, software, and applications in High-Performance Computing (HPC).  ...  The objective of the Eurolab-4-HPC vision is to provide a long-term roadmap from 2023 to 2030 for High-Performance Computing (HPC).  ...  The read latency and read energy of STT-RAM is expected to be comparable to that of SRAM.  ... 
arXiv:1807.04521v1 fatcat:5neetrgubjhnvcajcktpkohrzq

Resistive Crossbar-Aware Neural Network Design and Optimization

Muhammad Abdullah Hanif, Aditya Manglik, Muhammad Shafique
2020 IEEE Access  
Due to the aforementioned challenges associated with large crossbars (high IR drop and high read/write voltage requirements), we constrained the upper-limit of crossbar size as 512 × 512.  ...  Among the Non-Volatile Memory candidates, memristor-based Resistive RAM (ReRAM) offers high endurance (up to 10 10 cycles), fast switching and low read/write energy [54] - [56] .  ...  His research interests include design and critical analysis of high-performance computing (HPC) systems, focusing on exascale computation platforms and next-generation workloads such as ubiquitous machine  ... 
doi:10.1109/access.2020.3045071 fatcat:vezdek5fe5c5hdemui2qqu3bba

2021 Index IEEE Transactions on Electron Devices Vol. 68

2021 IEEE Transactions on Electron Devices  
-that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021.  ...  Note that the item title is found only under the primary entry in the Author Index.  ...  ., +, TED Aug. 2021 3838-3842 Stress Engineering as a Strategy to Achieve High Ferroelectricity in Thick Hafnia Using Interlayer.  ... 
doi:10.1109/ted.2021.3138305 fatcat:37sowz27xjc4bjhktlrldi2nja

Device-Circuit Co-Design Employing Phase Transition Materials for Low Power Electronics

Ahmedullah Aziz
2019
We evaluate the achievable voltage swing, energy-delay trade-off, and noise response for this novel device.  ...  We show that such selective transitions can also be used to improve other MRAM designs with separate read/write paths, avoiding the possibility of read-write conflicts.  ...  Therefore, to counter global variations, dynamic tuning of the reference is required. We propose an approach to change VGS-IMT dynamically according to the global process corner.  ... 
doi:10.25394/pgs.8982722.v1 fatcat:cjfbfdiwvvh25a5k6sv45ycymq

D8.3.2: Final technical report and architecture proposal

Ramnath Sai Sagar, Jesus Labarta, Aad van der Steen, Iris Christadler, Herbert Huber
2010 Zenodo  
This document describes the activities in Work Package 8 Task 8.3 (WP8.3) updating and analysing results reported in D8.3.1 for the different WP8 prototypes.  ...  The device requires connection to the mains to read voltage whereas current is measured using induction clamps.  ...  In contrast, Intel processors are known to have very high LINPACK efficiency with the latest HPCC entries achieving as high as 96 %.  ... 
doi:10.5281/zenodo.6546134 fatcat:35eigjqrzvb3vfd3pjud2oswtu

Amplitude-dependent properties of a hydrodynamic soliton

Junru Wu, Isadore Rudnick
1985 Physical Review Letters  
Thanks go to our numerous coworkers for extended times of discussion and exchange of ideas, in particular to Martin Wiesenfeldt and the Nonlinear Dynamics Group of the Drittes Physikalisches Institut,  ...  and feedback could give a high detectivity even with low mass.  ...  in order to construct acoustic microscopes yielding a resolution beyond the diffraction limit. 1617 Note added in proof: Recently, we became aware of research work carried out by two groups discussing  ... 
doi:10.1103/physrevlett.55.204 pmid:10032028 fatcat:kwodftbphjbd7ctg6rkenijptq

Enabling big memory with emerging technologies

Manjunath Shevgoor
2016
Crosspoint memories promise to greatly increase bit densities but have long read latencies because of sneak currents in the cross-bar.  ...  In the past, Dynamic Random Access Memory (DRAM) process scaling has enabled this increase in memory capacity.  ...  They also have read latencies that can be as low as 7.2 ns [118] and have better on/off resistance ratio than STT-RAM.  ... 
doi:10.26053/0h-ndgx-cmg0 fatcat:7egi5favrrhtfitkowb7b7ox2e

ETP4HPC's Strategic Research Agenda for High-Performance Computing in Europe 4 [article]

Michael Malms, Marcin Ostasz, Maike Gilliot, Pascale Bernier-Bruna, Laurent Cargemel, Estela Suarez, Herbert Cornelius, Marc Duranton, Benny Koren, Pascale Rosse-Laurent, María S. Pérez-Hernández, Manolis Marazakis (+11 others)
2020 Zenodo  
The main objective of this SRA is to identify the European technology research priorities in the area of HPC and High-Performance Data Analytics (HPDA), which should be used by EuroHPC to build its 2021  ...  This new concept well reflects the main trend of this SRA – it is not only about developing HPC technology in order to build competitive European HPC systems but also about making our HPC solutions work  ...  (STT-RAM) are interesting technologies, rallelism.  ... 
doi:10.5281/zenodo.4605343 fatcat:lcsgbea5dzgdfmj5dkw6pr7vni

Modal Analysis of Electric sail

Todd D. Lillian
2021 Acta Astronautica  
Gerald Karr, Brooke Graham, and Katie Hayden, for providing this unique opportunity to work with NASA researchers in a NASA environment. A special gratitude he gives to the MSFC Collaborators, Dr.  ...  We also would like to thanks engineers and scientists at NASA MSFC ES36 group who took time and shared their thoughts and ideas on using wireless sensor network technologies in space applications.  ...  Sufficient impulse margin must be allowed in order for the spacecraft to correct a higher-than-nominal energy level up on reaching the final burn initiation point or "high gate."  ... 
doi:10.1016/j.actaastro.2021.05.003 fatcat:haxb75tn2bd7xp43hw6hv4mlya
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