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Controller Synthesis for Mapping Partitioned Programs on Array Architectures [chapter]

Hritam Dutta, Frank Hannig, Jürgen Teich
2006 Lecture Notes in Computer Science  
This paper presents an efficient methodology for the automated control path synthesis for the mapping of partitioned algorithms onto processor arrays.  ...  Thus, efficient control path synthesis is one of the greatest challenges when compiling algorithms onto processor arrays.  ...  Furthermore, the expensive design process for ASICs calls for an automated synthesis of such accelerators in form of array architectures.  ... 
doi:10.1007/11682127_13 fatcat:2ri566quzneadmx7p6pwjhwgwa

Chlorophyll

Phitchaya Mangpo Phothilimthana, Tikhon Jelvis, Rohin Shah, Nishant Totla, Sarah Chasins, Rastislav Bodik
2013 Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI '14  
We developed Chlorophyll, a synthesis-aided programming model and compiler for the GreenArrays GA144, an extremely minimalist low-power spatial architecture that requires partitioning a program into fragments  ...  The Chlorophyll programming model allows programmers to provide their insight on program partitioning by specifying partial partitioning of data and computation.  ...  Third, applying program synthesis to large problems may not scale. Algorithms developed for program synthesis operate on whole programs, but not on decompositions of larger programs [39, 20, 35] .  ... 
doi:10.1145/2594291.2594339 dblp:conf/pldi/PhothilimthanaJSTCB14 fatcat:kxqmfqg275cevdfxcennhbi6sq

DEFACTO: A design environment for adaptive computing technology [chapter]

Kiran Bondalapati, Pedro Diniz, Phillip Duncan, John Granacki, Mary Hall, Rajeev Jain, Heidi Ziegler
1999 Lecture Notes in Computer Science  
This paper describes DEFACTO, an end-to-end design environment for developing applications mapped to adaptive computing architectures.  ...  At present, developing applications on most such systems requires low-level VHDL coding, and complex management of communication and control.  ...  Generating Control for the Partition The final program implementation cannot operate correctly without a control mechanism.  ... 
doi:10.1007/bfb0097941 fatcat:elpp746jnnfr5ellraoxcsod4i

HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform

Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
2002 Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02  
A new mapping flow and algorithms to partition hardware and software are proposed to generate implementation that best utilizes this architecture.  ...  Encouraging preliminary results are shown for automotive electronic control examples.  ...  We are grateful for the support of the SRC under contract 683.004 and the California Micro program and industrial sponsors, Fujitsu, Cadence, and Synplicity.  ... 
doi:10.1145/774814.774820 fatcat:o3jj557bxzhingtl3gjngdyyhi

HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform

Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
2002 Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02  
A new mapping flow and algorithms to partition hardware and software are proposed to generate implementation that best utilizes this architecture.  ...  Encouraging preliminary results are shown for automotive electronic control examples.  ...  We are grateful for the support of the SRC under contract 683.004 and the California Micro program and industrial sponsors, Fujitsu, Cadence, and Synplicity.  ... 
doi:10.1145/774789.774820 dblp:conf/codes/BaleaniGJPBS02 fatcat:c4hiw5nz5vhtvb6g4zagkrl4ua

Automatic compilation to a coarse-grained reconfigurable system-opn-chip

Girish Venkataramani, Walid Najjar, Fadi Kurdahi, Nader Bagherzadeh, Wim Bohm, Jeff Hammes
2003 ACM Transactions on Embedded Computing Systems  
This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and automatically map the application onto the Morphosys architecture.  ...  The mapping process is static and it involves operation scheduling, processor allocation and binding, and register allocation in the context of the Morphosys architecture.  ...  Each partition is then scheduled to execute on the CCUs and control for the partition is usually a finite state machine (FSM) that executes on the GPP.  ... 
doi:10.1145/950162.950167 fatcat:atgwub4vmnfmtekpsaxiot77ju

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

Girish Venkataramani, Walid Najjar, Fadi Kurdahi, Nader Bagherzadeh, Wim Bohm
2001 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01  
This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and map the application onto the Morphosys architecture.  ...  The mapping process involves operation scheduling, resource allocation and binding and register allocation in the context of the Morphosys architecture.  ...  This paper describes a compiler framework for mapping applications written in SA-C for execution on the Morphosys architecture.  ... 
doi:10.1145/502217.502235 dblp:conf/cases/VenkataramaniNKBB01 fatcat:rgrxe4bepzdu3ppwjqirb7pspu

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

Girish Venkataramani, Walid Najjar, Fadi Kurdahi, Nader Bagherzadeh, Wim Bohm
2001 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01  
This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and map the application onto the Morphosys architecture.  ...  The mapping process involves operation scheduling, resource allocation and binding and register allocation in the context of the Morphosys architecture.  ...  This paper describes a compiler framework for mapping applications written in SA-C for execution on the Morphosys architecture.  ... 
doi:10.1145/502231.502235 fatcat:2wolpe2czvbftpldhbnja6ukou

Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification

Pramod Chandraiah, Rainer Doemer
2007 Proceedings - Design Automation Conference  
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements.  ...  The immense potential available through MPSoC architectures depends heavily on the effectiveness of this programming.  ...  First, most rely on a shared memory programming model and hence cannot handle heterogeneous MPSoC architectures such as specialized custom processors and non-uniform memory architectures.  ... 
doi:10.1109/dac.2007.375271 fatcat:4ejtfp27a5b5ll4wkv3e2yzxvm

An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures [chapter]

Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
1998 Lecture Notes in Computer Science  
The system contains a temporal partitioning tool to temporally divide and schedule the tasks on the recon gurable architecture, a spatial partitioning tool to map the tasks to individual fpgas, and a high-level  ...  This paper presents an integrated design system called sparcs Synthesis and Partitioning for Adaptive Recon gurable Computing Systems for automatically partitioning and synthesizing designs for recongurable  ...  Approaches for temporal partitioning, spatial partitioning, and high-level synthesis geared towards recon gurable architectures were presented. sparcs system is continuing to develop towards handling large  ... 
doi:10.1007/3-540-64359-1_669 fatcat:zslppqtsk5bxrgapwyix4yfoxq

Designer-controlled generation of parallel and flexible heterogeneous MPSoC specification

Pramod Chandraiah, Rainer Doemer
2007 Proceedings - Design Automation Conference  
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements.  ...  The immense potential available through MPSoC architectures depends heavily on the effectiveness of this programming.  ...  First, most rely on a shared memory programming model and hence cannot handle heterogeneous MPSoC architectures such as specialized custom processors and non-uniform memory architectures.  ... 
doi:10.1145/1278480.1278676 dblp:conf/dac/ChandraiahD07 fatcat:kakplypynnavbab23f6xjfy5wq

Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs

Roberto Pérez-Andrade, César Torres-Huitzil, René Cumplido
2015 Microprocessors and microsystems  
In this paper a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model is presented.  ...  The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as support for solving problems independently of their size and  ...  Jose Juan Garcia for their discussions and comments about this research.  ... 
doi:10.1016/j.micpro.2014.12.003 fatcat:3nkmqtg3cjgudbi4ftcmqlwqwe

Modeling Loop Unrolling: Approaches and Open Issues [chapter]

João M. P. Cardoso, Pedro C. Diniz
2004 Lecture Notes in Computer Science  
Loop unrolling plays an important role in compilation for Reconfigurable Processing Units (RPUs) as it exposes operator parallelism and enables other transformations (e.g., scalar replacement).  ...  In Figure 1 we illustrate a generic compilation and synthesis flow for reconfigurable architectures.  ...  In general, existing efforts have focused on well-behaved loops i.e., loops without irregular control flow, and statically known iteration space, for which there is wealth of static program analysis information  ... 
doi:10.1007/978-3-540-27776-7_24 fatcat:77yfxj7zxvcc7bophw3p47d74a

Binary synthesis

Greg Stitt, Frank Vahid
2007 ACM Transactions on Design Automation of Electronic Systems  
to achieve results competitive with source-level synthesis, hardware/software partitioning methods necessary to find critical binary regions suitable for synthesis, synthesis methods for converting regions  ...  We compare binary synthesis to several related areas of research, and we then describe the key technologies required for effective binary synthesis: decompilation techniques necessary for binary synthesis  ...  For this example, the target architecture uses memory-mapped registers within the FPGA, allowing a move instruction to transfer data to these registers.  ... 
doi:10.1145/1255456.1255471 fatcat:ch3da4ypozfetgij2y2j6ecweq

Automatic FIR Filter Generation for FPGAs [chapter]

Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
2005 Lecture Notes in Computer Science  
PARO is a design system project for modeling, transformation, optimization, and synthesis of massively parallel VLSI architectures.  ...  Finally, synthesizable VHDL code is generated and mapped to an FPGA, the results are compared with a commercial filter generator.  ...  (Space-time mapping for co-partitioning).  ... 
doi:10.1007/11512622_7 fatcat:vifqb55j3jhu3k6nlu3zhbcjda
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