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Control techniques to eliminate voltage emergencies in high performance processors

R. Joseph, D. Brooks, M. Martonosi
The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.  
With the ITRS roadmap predicting aggressive drops in supply voltage and power supply impedances in coming chip generations, novel voltage control techniques will be required to stay on track.  ...  by the processor.  ...  Acknowledgements We would like to thank our colleagues in academia and industry for many stimulating discussions, as well as the anonymous reviewers for their useful comments and suggestions.  ... 
doi:10.1109/hpca.2003.1183526 dblp:conf/hpca/JosephBM03 fatcat:iidz7vncfnaonkysgnk3kmssti

Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization

Kim Hazelwood, David Brooks
2004 Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04  
voltage emergencies.  ...  Furthermore, a dynamic optimizer can eliminate the problem at run time, avoiding the difficult task of statically predicting voltage emergencies.  ...  Acknowledgments We would like to thank Russ Joseph for his guidance during the process of replicating his infrastructure and stressmark. This work was sponsored by a Harvard DEAS Fellowship.  ... 
doi:10.1145/1013235.1013315 dblp:conf/islped/HazelwoodB04 fatcat:w3ockqszwvgphllzxwjzxrsap4

Improved Output Voltage Quality using Space Vector Modulation for Multilevel Inverters

Auzani Jidin, Syamim Sanusi, Tole Sutikno, Nik Rumzi Nik Idris
2016 TELKOMNIKA (Telecommunication Computing Electronics and Control)  
Moreover, the proposed method utilizes two controller boards to perform high computational workloads and to eliminate glitch and error problems.  ...  to be implemented in vector control systems.  ...  For example, the SVM technique is widely adopted in motor drive systems to obtain excellent torque or speed control performance.  ... 
doi:10.12928/telkomnika.v14i2.3111 fatcat:whlpzkzd2fhijosq36mc7msvzy

An event-guided approach to reducing voltage noise in processors

M.S. Gupta, V.J. Reddi, G. Holloway, Gu-Yeon Wei, D.M. Brooks
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
A voltage "emergency", i.e., a swing beyond tolerable operating margins, jeopardizes the safe and correct operation of the processor.  ...  After tightening supply voltage margins to increase clock frequency and accounting for all costs, the net result is a performance improvement of 8% across a suite of fifteen SPEC CPU2000 benchmarks.  ...  ACKNOWLEDGMENTS We are grateful to our colleagues in industry and academia for the many discussions that have contributed to this work.  ... 
doi:10.1109/date.2009.5090651 dblp:conf/date/GuptaRHWB09 fatcat:joexhdrt3nha3mlmwtwikwaehu

Advanced power management techniques

Luca Benini
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
Well into the System-on-Chip era, power consumption has emerged as one of the most critical challenges to design complexity scaling.  ...  technologies and architectures, we survey the distinguishing features of a design methodology that aims at energy consumption reduction, under guaranteed quality of service (QoS), as a main objective in  ...  Power management has emerged as the most promising approach to tackle the power crisis, because it makes it possible to finely control the power-performance tradeoff at run time.  ... 
doi:10.1145/1119772.1119848 dblp:conf/aspdac/Benini03 fatcat:ursjrtyzdffofc5rulnopweas4

VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors

Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
One such challenge is increased sensitivity to voltage fluctuations, which can trigger so-called "voltage emergencies" that can lead to errors.  ...  We show that VRSync is very effective at eliminating emergencies, allowing voltage guardbands to be significantly lowered, which reduces energy consumption by an average of 33%.  ...  To prevent these emergencies, chip designers add voltage margins that in modern processors can be as high as 20% [12, 26] , leading to higher power consumption than necessary.  ... 
doi:10.1109/isca.2012.6237022 dblp:conf/isca/MillerTPT12 fatcat:gsoefknjuzeurcljr3ic4jspsq

Eliminating voltage emergencies via software-guided code transformations

Vijay Janapa Reddi, Simone Campanoni, Meeta S. Gupta, Michael D. Smith, Gu-Yeon Wei, David Brooks, Kim Hazelwood
2010 ACM Transactions on Architecture and Code Optimization (TACO)  
In recent years, circuit reliability in modern high-performance processors has become increasingly important.  ...  The proposed technique reassembles a traditional reliability problem as a runtime performance optimization problem, thus allowing us to design processors for typical case operation by building intelligent  ...  Our collaborative design is a more holistic technique for handling voltage emergencies, as compared to prior hardware techniques.  ... 
doi:10.1145/1839667.1839674 fatcat:uxznhy2dzfd5pbpqjvbxd5j6em

VRSync

Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu
2012 SIGARCH Computer Architecture News  
One such challenge is increased sensitivity to voltage fluctuations, which can trigger so-called "voltage emergencies" that can lead to errors.  ...  We show that VRSync is very effective at eliminating emergencies, allowing voltage guardbands to be significantly lowered, which reduces energy consumption by an average of 33%.  ...  To prevent these emergencies, chip designers add voltage margins that in modern processors can be as high as 20% [12, 26] , leading to higher power consumption than necessary.  ... 
doi:10.1145/2366231.2337188 fatcat:fxbxcnfx2rcz3cogqgsijg63tq

Towards a software approach to mitigate voltage emergencies

Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David Brooks
2007 Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07  
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors.  ...  emergencies in each important loop through simple observations and a simple priority function, and finally apply straightforward software optimization strategies to mitigate up to 70% of the future voltage  ...  [3] present a control-theoretic technique to handle the di/dt emergencies.  ... 
doi:10.1145/1283780.1283808 dblp:conf/islped/GuptaRSWB07 fatcat:u3a52ifxarccdoiaylencjphuy

Software-assisted hardware reliability

Vijay Janapa Reddi, Meeta S. Gupta, Michael D. Smith, Gu-yeon Wei, David Brooks, Simone Campanoni
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
Power constrained designs are becoming increasingly sensitive to supply voltage noise.  ...  The run-time layer removes 60% of these events with minimal overhead, thereby significantly improving overall performance.  ...  Acknowledgments We are grateful to Glenn Holloway and the anonymous reviewers for their comments and suggestions.  ... 
doi:10.1145/1629911.1630114 dblp:conf/dac/ReddiGSWBC09 fatcat:2znymncztnaf7nqv4l7m2emu7q

Thermal crisis: challenges and potential solutions

Li Shang, R.P. Dick
2006 IEEE potentials  
Acknowledgments We would like to thank Prof. Seda Ogrenci Memik for suggesting improvements to this article.  ...  When run-time thermal emergencies occur due to prolonged high power consumption, thermalaware control techniques are engaged to eliminate thermal emergencies by reducing the power consumption, and performance  ...  In addition, by controlling the operation of microchannels at hotspot regions, local thermal emergencies can be eliminated.  ... 
doi:10.1109/mp.2006.1692283 fatcat:lp7m4lkhuvbxrh4m3evjoawuci

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

Hyung-Beom Jang, Ik-Roh Yoon, Cheol-Hong Kim, Seung-Won Shin, Sung-Woo Chung
2012 JSTS Journal of Semiconductor Technology and Science  
In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling.  ...  For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length.  ...  Liquid Cooling Techniques Conventionally, 2D planar high-performance microprocessors have relied on the air cooling scheme to avoid the thermal emergency.  ... 
doi:10.5573/jsts.2012.12.3.297 fatcat:hxvqzug26bhexedpk7frxst57i

Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management

Changyun Zhu, Zhenyu Gu, Li Shang, R.P. Dick, R. Joseph
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The proposed technique is evaluated using multiprogrammed and multithreaded benchmarks in an integrated power, performance, and temperature full-system simulation environment.  ...  power characteristics and processor core thermal characteristics should be exploited; and 2) it proposes an efficient proactive continuously engaged hardware and operating system thermal management technique  ...  eliminate thermal emergencies.  ... 
doi:10.1109/tcad.2008.925793 fatcat:lzzujkiit5gxhlf5jcstwz5xoi

Microprocessors thermal challenges for portable and embedded systems using thermal throttling technique

Diary R. Sulaiman
2011 Procedia Computer Science  
When temperature is high, the presented method is considered to be the most effective technique.  ...  In this paper a thermal throttling technique is presented, that coordinates between processors thermal states and running states.  ...  Therefore, it is possible to integrate and use the thoughts of this technique with existing processor to study system level power and thermal issues for various high performance processors accurately.  ... 
doi:10.1016/j.procs.2010.12.168 fatcat:6fvolf55lbd67lujz6d5raiw54

Dynamically reducing overestimated design margin of MultiCores

Toshinori Sato, Takanori Hayashida, Ken Yano
2012 2012 International Conference on High Performance Computing & Simulation (HPCS)  
The combination of DVS (Dynamic voltage scaling) technique and Canary FF (flip-flop), named Canary-DVS, has been proposed to eliminate the overestimated voltage margin but has only been evaluated under  ...  MultiCore processor is one of the promising techniques to satisfy computing demands of the future consumer devices.  ...  The authors would like to thank Shunitsu Kohara of Toshiba Corporation for helping them use MeP simulator.  ... 
doi:10.1109/hpcsim.2012.6266944 dblp:conf/ieeehpcs/SatoHY12 fatcat:6fehue5wrnaznnd3pdg6aqhtai
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