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Control speculation in multithreaded processors through dynamic loop detection

J. Tubella, A. Gonzalez
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture  
We propose to apply this dynamic loop detection to the speculation of multiple threads of control dynamically obtained from a sequential program.  ...  We show that for a 4-context multithreaded processor, the speculation mechanism provides around 2.6 concurrent threads in average.  ...  When a new loop is executed, the proposed approach always inserts a new entry in both Control speculation in multithreaded processors In this section we show how to apply the previous scheme to dynamically  ... 
doi:10.1109/hpca.1998.650542 dblp:conf/hpca/TubellaG98 fatcat:smo2hqgnq5dqfljb3oysr6wxw4

Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture

David A. Zier, Ben Lee
2010 IEEE Transactions on Parallel and Distributed Systems  
This paper also discusses the relationships that loops have on one another, in particular, how loop nesting levels can be extended through procedures.  ...  One promising method of exploiting TLP is Dynamic Speculative Multithreading (D-SpMT), which extracts multiple threads from a sequential program without compiler support or instruction set extensions.  ...  The two earliest representative D-SpMT architectures are Dynamic Multithreading (DMT) [11] and Speculative Multithreaded Processors (SMPs) [36] .  ... 
doi:10.1109/tpds.2009.47 fatcat:67yggflhyzhuliigsax3in274q

Exploiting speculative thread-level parallelism on a SMT processor [chapter]

Pedro Marcuello, Antonio González
1999 Lecture Notes in Computer Science  
In this paper we present a run-time mechanism to simultaneously execute multiple threads from a sequential program on a simultaneous multithreaded (SMT) processor.  ...  The threads are speculative in the sense that they are created by predicting the future control flow of the program. Moreover, threads are not necessarily independent.  ...  The research described in this paper has been developed using the resources of the European Center for Parallelism of Barcelona (CEPBA).  ... 
doi:10.1007/bfb0100636 fatcat:2fgstvv4kza5rcq4rzqn3kcxfm

Speculative multithreaded processors

G.S. Sohi, A. Roth
2001 Computer  
A speculative multithreaded processor consists logically of replicated processing elements that coopera-  ...  Speculative Multithreaded Processors S emiconductor technologies-along with innovative computer architectures-have provided the bricks and mortar for building phenomenal improvements in processing speed  ...  Acknowledgments This work was supported in part by National Science Foundation grants MIP-9505853, CCR-9900584 and 0071924, donations from Intel and Sun Microsystems, the University of Wisconsin Graduate  ... 
doi:10.1109/2.917542 fatcat:fsdtjvtfsnheljrwckngvqg73m

Thread partitioning and value prediction for exploiting speculative thread-level parallelism

P. Marcuello, A. Gonzalez, J. Tubella
2004 IEEE transactions on computers  
In general, we find that spawning threads associated to loop iterations is the most effective technique.  ...  However, the efficiency of this execution model strongly depends on the performance of the control and data speculation techniques.  ...  The research described in this paper has been developed using the resources of the European Center for Parallelism of Barcelona (CEPBA).  ... 
doi:10.1109/tc.2004.1261823 fatcat:a2euq2as3ra7jihbmtoaw47cgy

Multithreading decoupled architectures for complexity-effective general purpose computing

Michael Sung, Ronny Krashinsky, Krste Asanović
2001 SIGARCH Computer Architecture News  
A proposal for a multithreaded decoupled control/access/execute architecture is presented as a platform for achieving high performance on general purpose workloads.  ...  This work investigates the possibility of using multithreading to overcome the loss of decoupling dependencies that represent the cause of this main limitation in decoupled architectures.  ...  This decoupling essentially allows dynamic loop unrolling when loop conditions can be determined ahead of time.  ... 
doi:10.1145/563647.563658 fatcat:fjmdpove5ravhclvctbfurz6im

Multi-Threaded Processors [chapter]

David Padua, Amol Ghoting, John A. Gunnels, Mark S. Squillante, José Meseguer, James H. Cownie, Duncan Roweth, Sarita V. Adve, Hans J. Boehm, Sally A. McKee, Robert W. Wisniewski, George Karypis (+29 others)
2011 Encyclopedia of Parallel Computing  
In contrast, the multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline.  ...  This survey paper explains and classifies the various multithreading techniques in research and in commercial microprocessors and compares multithreaded processors with chip multiprocessors.  ...  A loop detection scheme to dynamically detect loops without compiler or user intervention with the aim of obtaining multiple threads from a sequential program is presented in [94] .  ... 
doi:10.1007/978-0-387-09766-4_423 fatcat:heb3n2cfwnbi5nvxv5kvxd2xgm

Multithreaded Processors

T. Ungerer
2002 Computer journal  
In contrast, the multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline.  ...  This survey paper explains and classifies the various multithreading techniques in research and in commercial microprocessors and compares multithreaded processors with chip multiprocessors.  ...  A loop detection scheme to dynamically detect loops without compiler or user intervention with the aim of obtaining multiple threads from a sequential program is presented in [94] .  ... 
doi:10.1093/comjnl/45.3.320 fatcat:hlkkabuhrzhkrmuyqomzfmc6zm

Speculative Multithreaded Processors [chapter]

Gurindar S. Sohi, Amir Roth
2000 Lecture Notes in Computer Science  
Speculative multithreading is such a model, making it a leading candidate for implementation in future-generation processors.  ...  We expect to see two major forms of thread-level speculation: control-driven and data-driven.  ...  Acknowledgements This work was supported in part by National Science Foundation grants MIP-9505853 and CCR-9900584, donations from Intel and Sun Microsystems, the University of Wisconsin Graduate School  ... 
doi:10.1007/3-540-44467-x_23 fatcat:2ecvlteawzb57ek3hz57axiejy

A Survey on Thread-Level Speculation Techniques

Alvaro Estebanez, Diego R. Llanos, Arturo Gonzalez-Escribano
2016 ACM Computing Surveys  
In this work we introduce the technique, present a taxonomy of TLS solutions, and summarize and put into perspective the most relevant advances in this field.  ...  Thread-Level Speculation (TLS) is a promising technique that allows the parallel execution of sequential code without relying on a prior, compile-time dependence analysis.  ...  This paper is dedicated in loving memory of Dr. Agustín de Dios Hernández.  ... 
doi:10.1145/2938369 fatcat:yqqyjoaidvci3d4dyuw2jc2p2i

Speculative multithreaded processors

Pedro Marcuello, Antonio González, Jordi Tubella
1998 Proceedings of the 12th international conference on Supercomputing - ICS '98  
In this chapter, the importance of the partitioning mechanisms on the performance of speculative multithreaded processors is analyzed.  ...  Two families of these policies are studied in this chapter; in one of them, speculative threads are selected based on some heuristics whereas in the other, speculative threads are chosen through a deeper  ...  threads such as the works from the I-ACOMA A different heuristic is used by the Dynamic Multithreaded Processor[2] which speculates on loop and subroutine continuations and allows the speculative threads  ... 
doi:10.1145/277830.277850 dblp:conf/ics/MarcuelloGT98 fatcat:ytextja3bncehcdetvjtb5pvda

Compiler analysis for trace-level speculative multithreaded architectures

C. Molina, A. Gonzalez, J. Tubella
2005 9th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT'05)  
Trace-Level Speculative Multithreaded Processors exploit trace-level speculation by means of two threads working cooperatively.  ...  In this paper, we propose a static program analysis for identifying candidate traces to be speculated.  ...  The research described in this paper has been developed using the resources of the European Center for Parallelism of Barcelona and the resources of the Robotics and Vision Group of Tarragona.  ... 
doi:10.1109/interact.2005.6 dblp:conf/IEEEinteract/MolinaGT05 fatcat:ftekxt65zjf2lff7op5k6k33vu

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform

Perry H. Wang, John P. Shen, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore
2004 SIGARCH Computer Architecture News  
In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading  ...  The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread  ...  We also thank Ashok Seshadri, Anthony Mah, and Piyush Desai who assisted us in the emulation-based prototyping work.  ... 
doi:10.1145/1037947.1024411 fatcat:7m34jxhc7vfpvfia4r5o4pdpoe

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform

Perry H. Wang, John P. Shen, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore
2004 ACM SIGOPS Operating Systems Review  
In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading  ...  The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread  ...  We also thank Ashok Seshadri, Anthony Mah, and Piyush Desai who assisted us in the emulation-based prototyping work.  ... 
doi:10.1145/1037949.1024411 fatcat:bcmhsxjs4zfixl62fx5mxxcitq

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform

Perry H. Wang, John P. Shen, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore
2004 SIGPLAN notices  
In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading  ...  The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread  ...  We also thank Ashok Seshadri, Anthony Mah, and Piyush Desai who assisted us in the emulation-based prototyping work.  ... 
doi:10.1145/1037187.1024411 fatcat:frntjetjcvbadehs5j5et5lcgu
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