Filters








282 Hits in 2.5 sec

Control flow speculation in multiscalar processors

Q. Jacobson, S. Bennett, N. Sharma, J.E. Smith
Proceedings Third International Symposium on High-Performance Computer Architecture  
This paper focuses on mechanisms to implement intertask control flow speculation (task prediction) in a Multiscalar implementation.  ...  In the Multiscalar hardware, a global sequencer, with help from the compiler, takes large steps through the program's control flow graph (CFG) speculatively, starting a new thread of control (task) at  ...  Vijaykumar for developing the multiscalar compiler.  ... 
doi:10.1109/hpca.1997.569673 dblp:conf/hpca/JacobsonBSS97 fatcat:io2cowc5gzcknaxwtuji27qnsm

A survey of new research directions in microprocessors

J. Šilc, T. Ungerer, B. Robic
2000 Microprocessors and microsystems  
Superspeculative processors also speculate about control dependences.  ...  Multiscalar and trace processors define several processing cores that speculatively execute different parts of a sequential program in parallel.  ...  In particular, task size affects load imbalance and overhead, inter-task control flow influences control speculation, and inter-task data dependence impacts data communication and data dependence speculation  ... 
doi:10.1016/s0141-9331(00)00072-7 fatcat:55y6n4wzijaeppl3l5qp6x2koa

Task Selection for the Multiscalar Architecture

T.N. Vijaykumar, Gurindar S. Sohi
1999 Journal of Parallel and Distributed Computing  
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential programs without impeding  ...  Abstract The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential programs without  ...  important factor in control flow speculation.  ... 
doi:10.1006/jpdc.1999.1557 fatcat:k2pxrq2nurdolfpq7bugizc4ca

Multiscalar processors

Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
1995 SIGARCH Computer Architecture News  
This paper presents the philosophy of the multi scalar paradigm, the structure of multiscalar programs, and the hardware architecture of a multiscalar processor.  ...  Memory accesses may occur speculatively without knowledge of preceding loads or stores. Addresses are disambiguated dynamically, many in parallel, and processing waits only for true data dependence.  ...  We would like to thank Jim Smith for his contributions to the multiscalar project in general, and this paper in particular.  ... 
doi:10.1145/225830.224451 fatcat:55gupm24cnhkhd7utva32dqwqu

Multiscalar processors

Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
This paper presents the philosophy of the multi scalar paradigm, the structure of multiscalar programs, and the hardware architecture of a multiscalar processor.  ...  Memory accesses may occur speculatively without knowledge of preceding loads or stores. Addresses are disambiguated dynamically, many in parallel, and processing waits only for true data dependence.  ...  We would like to thank Jim Smith for his contributions to the multiscalar project in general, and this paper in particular.  ... 
doi:10.1145/285930.286010 dblp:conf/isca/SohiBV98 fatcat:tba7kr7pkbb6viigq73o57k5pq

Trace processors: moving to fourth-generation microarchitectures

J.E. Smith, S. Vajapeyam
1997 Computer  
The authors describe some of the ways these processors will meet future technology demands.  ...  Trace processors rely on hierarchy, replication, and prediction to dramatically increase the execution speed of ordinary sequential programs.  ...  Acknowledgments We thank Guri Sohi for many enlightening and stimulating discussions on advanced high-ILP processors.  ... 
doi:10.1109/2.612251 fatcat:u6ntlnrvdrei5pmxcbnv7nmghe

Multiscalar processors

Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
1995 Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95  
This paper presents the philosophy of the multi scalar paradigm, the structure of multiscalar programs, and the hardware architecture of a multiscalar processor.  ...  Memory accesses may occur speculatively without knowledge of preceding loads or stores. Addresses are disambiguated dynamically, many in parallel, and processing waits only for true data dependence.  ...  We would like to thank Jim Smith for his contributions to the multiscalar project in general, and this paper in particular.  ... 
doi:10.1145/223982.224451 dblp:conf/isca/SohiBV95 fatcat:tdhpug2w5be4bgpluwrdi4elt4

Dynamic speculation and synchronization of data dependences

Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
1997 SIGARCH Computer Architecture News  
Experimental results evaluating the effectiveness of the proposed techniques are presented within the context of a Multiscalar processor.  ...  Data dependence speculation is used in instruction-level parallel (ILP) processors to allow early execution of an instruction before a logically preceding instruction on which it may be data dependent.  ...  Acknowledgments This work was supported in part by NSF Grants CCR-9303030 and MIP-9505853, ONR Grant N00014-93-1-0465, and by U.S.  ... 
doi:10.1145/384286.264189 fatcat:uz6shixsqbfq3bons5l7ff7pr4

Dynamic speculation and synchronization of data dependences

Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
1997 Proceedings of the 24th annual international symposium on Computer architecture - ISCA '97  
Experimental results evaluating the effectiveness of the proposed techniques are presented within the context of a Multiscalar processor.  ...  Data dependence speculation is used in instruction-level parallel (ILP) processors to allow early execution of an instruction before a logically preceding instruction on which it may be data dependent.  ...  Acknowledgments This work was supported in part by NSF Grants CCR-9303030 and MIP-9505853, ONR Grant N00014-93-1-0465, and by U.S.  ... 
doi:10.1145/264107.264189 dblp:conf/isca/MoshovosBVS97 fatcat:flejodcmjnglhg3xrb775gwvva

A Review on Superscalar Technology with instruction level parallelism (ILP) for Faster Microprocessor

Mr. Chirag R. Patel
2018 International Journal for Research in Applied Science and Engineering Technology  
Only one instruction is issued per cycle, and only one completion of instruction is expected from the pipeline per cycle per .In superscalar processor, multiple instructions are issued per cycle and multiple  ...  A CISC or a RISC scalar processor can be improved with a superscalar or vector architecture. Scalar processor is those executing one instruction per cycle.  ...  Many integer workloads feature complex control-flows whereby the outcome of a branch is affected by the outcomes of recently executed branches.  ... 
doi:10.22214/ijraset.2018.3337 fatcat:lqf54zvz3zcchbs2gmbzbr3eja

Exploiting speculative thread-level parallelism on a SMT processor [chapter]

Pedro Marcuello, Antonio González
1999 Lecture Notes in Computer Science  
The threads are speculative in the sense that they are created by predicting the future control flow of the program. Moreover, threads are not necessarily independent.  ...  In this paper we present a run-time mechanism to simultaneously execute multiple threads from a sequential program on a simultaneous multithreaded (SMT) processor.  ...  The research described in this paper has been developed using the resources of the European Center for Parallelism of Barcelona (CEPBA).  ... 
doi:10.1007/bfb0100636 fatcat:2fgstvv4kza5rcq4rzqn3kcxfm

A study of control independence in superscalar processors

E. Rotenberg, Q. Jacobson, J. Smith
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors.  ...  It is shown that much of the performance potential of control independence is lost due to data dependences and wasted resources consumed by incorrect control dependent instructions.  ...  Acknowledgments This work was supported in part by NSF Grant MIP-9505853 and by the U.S. Army Intelligence Center and Fort Huachuca under Contract DABT63-95-C-0127 and ARPA order no. D346.  ... 
doi:10.1109/hpca.1999.744346 dblp:conf/hpca/RotenbergJS99 fatcat:ns45qyk5wzglnayipgcacseine

Clustered speculative multithreaded processors

Pedro Marcuello, Antonio González
1999 Proceedings of the 13th international conference on Supercomputing - ICS '99  
Spawning a speculative thread involves predicting its control flow as well as its dependences with other threads and the values that flow through them.  ...  Control-flow, data value and data dependence predictors particularly designed for this type of microarchitecture are presented.  ...  The research described in this paper has been developed using the resources of the European Center of Parallelism of Barcelona (CEPBA).  ... 
doi:10.1145/305138.305214 dblp:conf/ics/MarcuelloG99 fatcat:4osvinevx5fongtizk2uuvcjje

Compiler optimization of scalar value communication between speculative threads

Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, Todd C. Mowry
2002 SIGPLAN notices  
In addition, we contrast our compiler techniques with related hardware-only approaches.  ...  While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for  ...  In contrast, our speculative threads (aka epochs) are much larger on average than Multiscalar tasks and contain complex control flow.  ... 
doi:10.1145/605432.605416 fatcat:6m5zl6vvinfo7cn3uxoa3gjo4m

Compiler optimization of scalar value communication between speculative threads

Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, Todd C. Mowry
2002 Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international conference on architectural support for programming languages and operating systems (ASPLOS-X) - ASPLOS '02  
In addition, we contrast our compiler techniques with related hardware-only approaches.  ...  While there have been many recent proposals for hardware that supports Thread-Level Speculation (TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for  ...  In contrast, our speculative threads (aka epochs) are much larger on average than Multiscalar tasks and contain complex control flow.  ... 
doi:10.1145/605397.605416 dblp:conf/asplos/ZhaiCSM02 fatcat:auohm6qqfvebzbikrydspfus7a
« Previous Showing results 1 — 15 out of 282 results