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A Study on Applying Parallelism for Construction of Steiner Tree Algorithms in VLSI Design

Shyamala G., Latha N.
2016 International Journal of Computer Applications  
We present a survey of the different approaches that can be parallelized and also the parallel algorithms available today with special concern to Rectilinear steiner tree for VLSI Design and their appropriateness  ...  Here, we present a survey of the parallel methods for solving the stiener tree problem specifically for VLSI design General Terms Multicore Architecture, Parallel computing, VLSI  ...  Rectilinear Steiner tree One of the important purpose of Steiner tree in electronic design automation is in placement and routing stage of VLSI design process.  ... 
doi:10.5120/ijca2016911006 fatcat:i7y4vwl2w5fetigheio2tl4l3q

Applications of network coding in global routing

Nikhil Nemade, Alex Sprintson, Jiang Hu
2009 2009 IEEE International Conference on IC Design and Technology  
We study the applications of the network coding technique for interconnect optimization and improving the routability of VLSI designs.  ...  While the traditional methods of interconnect routing have attracted a large body of research, applications of network coding in VLSI design have received a relatively little interest from the research  ...  The length of a Steiner tree is equal to the sum of the lengths of its vertical and horizontal segments. A Rectilinear Steiner Minimum Tree (RSMT) is a rectilinear Steiner tree of minimum length.  ... 
doi:10.1109/icicdt.2009.5166264 fatcat:vuwdajx24zgadp2pgw7353b5oy

An Improved Augmented Line Segment based Algorithm for the Generation of Rectilinear Steiner Minimum Tree

Vani V, G.R. Prasad
2017 International Journal of Electrical and Computer Engineering (IJECE)  
Rectilinear Steiner Minimum Tree has the main application in the global routing phase of VLSI design.  ...  An improved Augmented Line Segment Based (ALSB) algorithm for the construction of Rectilinear Steiner Minimum Tree using augmented line segments is proposed.  ...  Rectilinear Steiner Minimum Tree construction is one of the fundamental problems that have many applications in VLSI design. It can be used figure 2 .  ... 
doi:10.11591/ijece.v7i3.pp1262-1267 fatcat:dqnh7vpebff6xcsxfjnkybnsnu

Approximation of Rectilinear Steiner Trees with Length Restrictions on Obstacles [chapter]

Matthias Müller-Hannemann, Sven Peyer
2003 Lecture Notes in Computer Science  
This kind of length restriction is motivated by its application in VLSI design where a large Steiner tree requires the insertion of buffers (or inverters) which must not be placed on top of obstacles.  ...  We consider the problem of finding a shortest rectilinear Steiner tree for a given set of points in the plane in the presence of rectilinear obstacles.  ...  The motivation to study the length-restricted Steiner tree problem stems from its application in the construction of buffered routing trees in VLSI design [1], [2], [7] .Consider a situation where we  ... 
doi:10.1007/978-3-540-45078-8_19 fatcat:xswrivkainebbbvssernd6ymu4

Rectilinear group Steiner trees and applications in VLSI design

Martin Zachariasen, André Rohe
2003 Mathematical programming  
This is an important generalization of the well-known rectilinear Steiner tree problem which has direct applications in VLSI design, i.e., it is the fundamental problem that has to be solved in the detailed  ...  The reductions of the Hanan grid are performed by applying point deletions and by generating full Steiner trees on the remaining points.  ...  We thank Sven Peyer, David Pisinger, Jens Vygen and J urgen Werber for reading and commenting on drafts of this paper.  ... 
doi:10.1007/s10107-002-0326-x fatcat:desqqizssnbmvojcwvpdclfohy

Preferred direction Steiner trees

Mehmet Can Yildiz, Patrick H. Madden
2001 Proceedings of the 11th Great Lakes Symposium on VLSI - GLSVLSI '01  
ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their comments and suggestions; one reviewer pointed out a deviation in our algorithm from the original work of Borah et al.,  ...  and this was particularly helpful.  ...  Many current planar rectilinear approaches rely heavily on the Hanan grid to reduce the size of the solution space; nonlinear costs and preferred direction constraints may suggest that this grid no longer  ... 
doi:10.1145/368122.368797 dblp:conf/glvlsi/YildizM01 fatcat:sy3stahperf43ldzryvb6oofqa

Preferred direction Steiner trees

M.C. Yildiz, P.H. Madden
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their comments and suggestions; one reviewer pointed out a deviation in our algorithm from the original work of Borah et al.,  ...  and this was particularly helpful.  ...  Many current planar rectilinear approaches rely heavily on the Hanan grid to reduce the size of the solution space; nonlinear costs and preferred direction constraints may suggest that this grid no longer  ... 
doi:10.1109/tcad.2002.804105 fatcat:kc2hyormzravzeq3cui77skx4i

Timing-Driven Interconnect Synthesis [chapter]

Jiang Hu, Gabriel Robins, Cliff Sze
2008 Handbook of Algorithms for Physical Design Automation  
., Steiner) interconnect trees, especially as die sizes continue to grow while feature dimensions steadily shrink. 1 The exposition below focuses on selected approaches to performance-driven routing, and  ...  On the other hand, modern ultra-deep-submicron VLSI CAD seeks to optimize and tradeoff various combinations of objectives and criteria, such as delay,  ...  Steiner Arborescences Historically, the primary application of rectilinear Steiner minimum trees in VLSI CAD has been in global routing, since older physical design paradigms did not require the modeling  ... 
doi:10.1201/9781420013481.ch25 fatcat:hprn5yjm4balzg3poc4f3q6ifm

Performance Analysis of the Algorithms for the Construction of Rectilinear Steiner Minimum Tree

2013 IOSR Journal of VLSI and Signal processing  
The problem of finding Rectilinear Steiner Minimum Tree is one of the fundamental problems in the field of electronic design automation.  ...  Rectilinear Steiner Minimum Tree is widely used in global routing phase of VLSI design and wire length estimation.  ...  Fig. 1 1 Fig. 1 Rectilinear Steiner Minimum Tree Fig. 2 Hanan Grid and Minimum Spanning Tree www.iosrjournals.org  ... 
doi:10.9790/4200-0336168 fatcat:xkrykxlrbvh65b3glmiezmdt74

An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments

Ming Che Lee, Gene Eu Jan, Chung Chin Luo
2020 IEEE Access  
The rectilinear/octilinear Steiner problem is the problem of connecting a set of terminals Z using orthogonal and diagonal edges with minimum length.  ...  This problem has many applications, such as the EDA, VLSI circuit design, fault-tolerant routing in mesh-based broadcast, and Printed Circuit Board (PCB).  ...  FIGURE 5 . 5 An example of rectilinear grid (a) Rectilinear grid with terminals T1∼T5 (b) Hanan Grid and Hanan vertices.  ... 
doi:10.1109/access.2020.2977825 fatcat:il2zkodgznephfq65d2wxcbgqi

Minimum Steiner Tree Construction* [chapter]

Gabriel Robins, Alexander Zelikovsky
2008 Handbook of Algorithms for Physical Design Automation  
broader overview of the field of computer-aided design of VLSI is given by several textbooks on this subject [34, 71, 81, 84, 85] .  ...  |x 1 − x 2 | + |y 1 − y 2 | We will focus on the rectilinear Steiner minimal tree problem, where every edge is embedded in the plane using a path of one or more alternating horizontal and vertical segments  ...  Rather, it focuses on a few selected results and approaches to Steiner tree construction.  ... 
doi:10.1201/9781420013481.ch24 fatcat:r2ewkzgdebhypbvn2v3f7vrya4

Obstacle aware delay optimized rectilinear steiner minimum tree routing

Shyamala G, G R Prasad
2019 Indonesian Journal of Electrical Engineering and Computer Science  
<p><span>This work presents a method to solve the problem of constructing Rectilinear Steiner Minimum Tree (RSMT) for a group of pins in the presence of obstacles.  ...  This work presents an Obstacle Aware Delay Optimized Rectilinear Steiner Minimum Tree (OADORSMT) Routing to address the delay, slew constraint and reduce the routing resources.  ...  The modified Hanan grids consist of escaping graph and Hanan grids. Extending Hanan grid may not solve LRSMT problem.  ... 
doi:10.11591/ijeecs.v16.i2.pp640-652 fatcat:kc5f2gudynhljbrngr4wjo4x4u

A new heuristic for rectilinear Steiner trees

I.I. Mandoiu, V.V. Vazirani, J.L. Ganley
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Thus, nding a minimum rectilinear Steiner tree on a set of terminals reduces to nding a minimum Steiner tree in the Hanan grid, with edge costs given by the L1 (or Manhattan) metric, d(u v) = jxu;xvj+jyu  ...  Introduction The Steiner tree problem is that of nding a minimum-length interconnection of a set of points in the plane, and has long been one of the fundamental problems in the eld of electronic design  ... 
doi:10.1109/43.875292 fatcat:gkoom3s3nvdytcvfjhufixwoyu

Circuit simulation based obstacle-aware Steiner routing

Yiyu Shi, Paul Mesa, Hao Yu, Lei He
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields.  ...  We show that the faster an output reaches its peak, the higher the possibility for the correspondent Hanan node to be a Steiner point.  ...  INTRODUCTION Rectilinear Steiner minimum tree (RSMT) construction is a fundamental research problem in VLSI design.  ... 
doi:10.1145/1146909.1147011 dblp:conf/dac/ShiMYH06 fatcat:3ymatvwyd5f45lfrlfqyz3owbq

Circuit simulation based obstacle-aware Steiner routing

Yiyu Shi, P. Mesa, Hao Yu, Lei He
2006 Proceedings - Design Automation Conference  
Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields.  ...  We show that the faster an output reaches its peak, the higher the possibility for the correspondent Hanan node to be a Steiner point.  ...  INTRODUCTION Rectilinear Steiner minimum tree (RSMT) construction is a fundamental research problem in VLSI design.  ... 
doi:10.1109/dac.2006.229212 fatcat:rhwh36m4lvgb5f7wvmyz6lbghq
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