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Optimal algorithms for the channel-assignment problem on a reconfigurable array of processors with wider bus networks

Shi-Jinn Horng, Horng-Ren Tsai, Yi Pan, J. Seitzer
2002 IEEE Transactions on Parallel and Distributed Systems  
For the channel-assignment problem with N pairs of components, we first design an OðT þ d N w eÞ time parallel algorithm using 2N processors with a 2N-row by 2N-column bus network, where the bus width  ...  The computation model on which the algorithms are developed is the reconfigurable array of processors with wider bus networks (abbreviated to RAPWBN).  ...  Lin [14] also gave an Oð1Þ time parallel algorithm for this problem on the processor arrays with reconfigurable bus systems using OðN 2 Þ processors.  ... 
doi:10.1109/tpds.2002.1058096 fatcat:fepjicxp4zbjjnxugke5gbwopy

Architectures for supersystems of the '80s

Svetlana P. Kartashev, Steven I. Kartashev
1980 Proceedings of the May 19-22, 1980, national computer conference on - AFIPS '80  
Thus a fast processor bus may be organized without connecting elements. The time of reconfiguration of such bus will be entirely dependent on the time of accessing new control codes.  ...  The systems which possess an extreme computational power and are capable of solving such problems will be called Supersystems. The problems for Supersystems may be non-real-time and real-time.  ... 
doi:10.1145/1500518.1500547 dblp:conf/afips/KartashevK80 fatcat:nxthadsuvfcjzlmjnkakmaia5m

Realizing reconfigurable mesh algorithms on softcore arrays

Heiner Giefers, Marco Platzner
2008 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation  
The reconfigurable mesh is a very popular model for massively parallel computation for which a large body of algorithms with exceptionally low runtime complexities exists.  ...  In this paper, we present the mapping of reconfigurable mesh algorithms to softcore arrays.  ...  A more general model extending the RMESH by three additional communication patterns is the Processor Array with Reconfigurable Bus System (PARBS) [7] .  ... 
doi:10.1109/icsamos.2008.4664845 dblp:conf/samos/GiefersP08 fatcat:353d4qdnxjgafpgkes6vymuzpm

Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs

Roberto Pérez-Andrade, César Torres-Huitzil, René Cumplido
2015 Microprocessors and microsystems  
In this paper a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model is presented.  ...  The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as support for solving problems independently of their size and  ...  Acknowledgments First author thanks the National Council for Science and Technology from Mexico (CONACyT) for financial support through the scholarship 3792, and to Dr. Manuel E. Guzman and Dr.  ... 
doi:10.1016/j.micpro.2014.12.003 fatcat:3nkmqtg3cjgudbi4ftcmqlwqwe

Processor arrays generation for matrix algorithms used in embedded platforms

Roberto Perez-Andrade, Cesar Torres-Huitzil, Rene Cumplido, Juan M. Campos
2013 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)  
This paper presents a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model.  ...  The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as it provides support for solving a set of problem size depending  ...  ACKNOWLEDGMENTS First author thanks the National Council for Science and Technology from Mexico (CONACyT) for financial support through the scholarship 3792, and to Dr. Manuel E.  ... 
doi:10.1109/reconfig.2013.6732322 dblp:conf/reconfig/Perez-AndradeTCC13 fatcat:7dxyl2u6nrgfjfeiojqpe42uiq

On reconfgurable co-processing units [chapter]

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1998 Lecture Notes in Computer Science  
In this paper important topics for reconfigurable platforms in multitasking systems are discussed.  ...  Besides the underlying concepts the hardware implementation of a fieldprogrammable ALU array (FPAA), the KrAA-III, is explained.  ...  To make such multitasking systems possible on reconfigurable structures, the following conditions must be met: Very short configuration times are required.  ... 
doi:10.1007/3-540-64359-1_675 fatcat:kx3ftnykpzbb3kh23xrpw2ovau

The Chimaera reconfigurable functional unit

S. Hauck, T.W. Fry, M.M. Hosler, J.P. Kao
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we describe Chimaera, a system that overcomes the communication bottleneck by integrating reconfigurable logic into the host processor itself.  ...  Index Terms-Adaptive systems, field-programmable gate arrays (FPGAs), reconfigurable architectures.  ...  running on a system, they provide performance gains for a much larger class of problems.  ... 
doi:10.1109/tvlsi.2003.821545 fatcat:lfoeqmq2lvbl3l3dckzioxehx4

Selective optical broadcasting in reconfigurable multiprocessor interconnects

Iñigo Artundo, Lieven Desmet, Wim Heirman, Christof Debaes, Joni Dambre, Jan Van Campenhout, Hugo Thienpont, Hugo Thienpont, Mohammad R. Taghizadeh, Peter Van Daele, Jürgen Mohr
2006 Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration  
the use of low cost, scalable and reconfigurable networks to resolve the problem.  ...  In this paper, we make an initial evaluation of the performance gain on general network reconfigurability.  ...  ACKNOWLEDGEMENTS The authors thank all members of the PMMA group at the Dept. of Applied Physics and Photonics in the Vrije Universiteit Brussel (VUB) for collaboration and research in recent years on  ... 
doi:10.1117/12.662882 fatcat:cvtw6b7ufvbsveluqehnt7u7je

HERMIA: An Heterogeneous and Reconfigurable Machine for Image Analysis

Gaetano Gerardi, Franco Chiavetta, Vito Di Gesù, Domenico Tegolo
1990 IAPR International Workshop on Machine Vision Applications  
The LLP module is dedicated to low level Heterogeneous and Reconfigurable Machine for Image the ILP performs the intermediate Analysis (HERMIA); the first prototype of the system has the performs high  ...  and been developed at the University of Palermo. interpretative analysis; the last one is also responsible for Conventional hardware has been used in order to emulate the management (operating system tasks  ...  Reconfigurability seems to be one of the key-features in the solution of vision problems [1, 2] .  ... 
dblp:conf/mva/GerardiCGT90 fatcat:cru33emkg5gzrec6abifuuqpeq

A SIMD SOLUTION TO BIOSEQUENCE DATABASE SCANNING

BERTIL SCHMIDT, HEIKO SCHRÖDER, THAMBIPILLAI SRIKANTHAN
2002 Parallel Computing  
Even though efficient dynamic programming algorithms exist for the problem, the required scanning time is still very high, and because of the exponential database growth finding fast solutions is of highest  ...  In this paper we present an approach to high-speed biosequence database scanning on the Fuzion 150, a new parallel computer with a linear SIMD array of 1536 processing elements on a single chip.  ...  Reconfigurable systems are based on programmable logic such as field-programmable gate arrays (FPGAs) or custom-designed arrays.  ... 
doi:10.1142/9781860949630_0029 fatcat:jk6w2as64zhfdlwwoeenklyk3a

High Performance Reconfigurable Computing Systems [article]

Issam Damaj
2019 arXiv   pre-print
Many other implementation options present, for instance, a system with a RISC processor and a DSP core. Other options include graphics processors and microcontrollers.  ...  The focus of this chapter is on introducing reconfigurable computers as modern super computing architectures.  ...  An overall decode performance improvement of 7.5 times for AVA has been achieved versus algorithm implementation on a Celeron-processor based system.  ... 
arXiv:1904.04953v1 fatcat:k5y4cpudi5e6dfqtpizj3z45te

A reconfigurable computing platform for plume tracking with mobile sensor networks

Byung Hwa Kim, Colin D'Souza, Richard M. Voyles, Joel Hesch, Stergios I. Roumeliotis, Grant R. Gerhart, Charles M. Shoemaker, Douglas W. Gage
2006 Unmanned Systems Technology VIII  
The system provides static and dynamic reconfigurability for both software and hardware by the combination of CPU (central processing unit) and FPGA (field-programmable gate array) allowing on-the-fly  ...  Static reconfigurability of the hardware manifests itself in the form of a "morphing bus" architecture that permits the modular connection of various sensors with no bus interface logic.  ...  The authors wish to thank Alliant Techsystems for discussions and sensors.  ... 
doi:10.1117/12.668961 fatcat:ellix4fzlfgttk5l6apsjas75u

A performance evaluation of the software-implemented fault-tolerancecomputer

D. L. PALUMBO, R. W. BUTLER
1986 Journal of Guidance Control and Dynamics  
Together with other system overhead (e.g., voting and scheduling), the operating system overhead is in excess of 60%.  ...  Using SIFT's specimen task load, the executive tasks, such as reconfiguration, clock synchronization, and interactive consistency, are found to consume significant computing resources.  ...  The exact time for reconfiguration depends on the number of working processors; however, the worst case is 35.19 ms or 11 subframes (see Fig. 6 ).  ... 
doi:10.2514/3.20087 fatcat:rawuqrhaovaj3hsunwi57bucfu

Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor

K.s. Tham, D.L. Maskell
2006 2006 International Conference on Field Programmable Logic and Applications  
for reconfigurable systems.  ...  Such reconfigurable systems present a difficult problem for current modeling platforms as a tightly-coupled co-design/simulation effort for both hardware and software must be integrated in the framework  ...  • MicroBlaze extension with custom functions To use the custom functions shown in Figure 3-15(b) directly, we can assign two FSL write channels for 'dcitaA' and 'dataB' bus that are each 32-bit wide  ... 
doi:10.1109/fpl.2006.311230 dblp:conf/fpl/ThamM06 fatcat:jyvrwl33uzcytolxwgywctvmwm

Novel Techniques for Processing Unstructured Data Sets

R.D. Chamberlain, R.K. Cytron
2005 2005 IEEE Aerospace Conference  
We now store much more data than we have time to process, implying that techniques for processing these data need to be significantly altered.  ...  While improvements in the density of semiconductor circuitry have been dramatic, the density improvements in magnetic storage have been even greater.  ...  At the same time interconnect and bus technology performance gains have not kept up with either.  ... 
doi:10.1109/aero.2005.1559609 fatcat:oowxqq362jfyxglmzmwp34zjee
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