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2021 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 68

2021 IEEE Transactions on Circuits and Systems - II - Express Briefs  
The Author Index contains the primary entry for each item, listed under the first author's name.  ...  -that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021.  ...  ., +, TCSII A 52-58 GHz Power Amplifier With 18.6-dBm Saturated Output Power for Jan. 2021 426-430 Space Applications.  ... 
doi:10.1109/tcsii.2022.3144928 fatcat:bm53w7gva5bthholfhhiq4yg3a

Low Power and Energy Efficient Asynchronous Design

Peter A. Beerel, Marly E. Roncken
2007 Journal of Low Power Electronics  
This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts.  ...  Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains  ...  We also thank Ivan Sutherland for helping us use the terms "energy" and "power" consistently, and for accepting-to his regret-our use of "open" and "closed" for latches.  ... 
doi:10.1166/jolpe.2007.138 fatcat:erlvur724ngp7bzbuluf2yn3se

A Digital Feedback System for Advanced Ion Manipulation Techniques in Penning Traps [article]

Jost Herkenhoff, Menno Door, Pavel Filianin, Wenjia Huang, Kathrin Kromer, Daniel Lange, Rima X. Schüssler, Christoph Schweiger, Sergey Eliseev, Klaus Blaum
2021 arXiv   pre-print
The possibility to apply active feedback to a single ion in a Penning trap using a fully digital system is demonstrated.  ...  The presented system is implemented using an FPGA-based platform (STEMlab), offering greater flexibility, higher temporal stability and the possibility for highly dynamic variation of feedback parameters  ...  The input and output amplifiers require a bipolar low-noise supply with ±5 V.  ... 
arXiv:2110.01404v1 fatcat:2sy6m6cljzgqfaxbuwckvg5bmu

A 72 × 60 Angle-Sensitive SPAD Imaging Array for Lens-less FLIM

Changhyuk Lee, Ben Johnson, TaeSung Jung, Alyosha Molnar
2016 Sensors  
The combination enables mapping of fluorescent sources with different lifetimes in 3D space down to micrometer scale.  ...  We present a 72 × 60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3D fluorescence lifetime imaging.  ...  (RO), Done[0:2] is a digital bit to power gate the RO to enable the low power DTC operation.  ... 
doi:10.3390/s16091422 pmid:27598170 pmcid:PMC5038700 fatcat:dmqjx2oimjbt5bijvvryie462y

A digital feedback system for advanced ion manipulation techniques in Penning traps

Jost Herkenhoff, Menno Door, Pavel Filianin, Wenjia Huang, Kathrin Kromer, Daniel Lange, Rima X. Schüssler, Christoph Schweiger, Sergey Eliseev, Klaus Blaum
2021 Review of Scientific Instruments  
The possibility of applying active feedback to a single ion in a Penning trap using a fully digital system is demonstrated.  ...  The presented system is implemented using a field-programmable gate array (FPGA)-based platform (STEMlab), offering greater flexibility, higher temporal stability, and the possibility for highly dynamic  ...  The input and output amplifiers require a bipolar low-noise supply with ±5 V.  ... 
doi:10.1063/5.0064369 pmid:34717400 fatcat:f6ijxtycmvhzdnswld5f2jzoqe

Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation

Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu
2013 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 90nm nodes with less than a 5% error.  ...  A systematic emulation approach to map any analog transistor to PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for I D and less than 10% for R out and G m .  ...  to use a simple digital delay-locked loop (DLL) to synchronize the clock with output data.High-performance GDDR4 SDRAMs have progressed from these previous generations by pushing speeds up to multi-giga-hertz  ... 
doi:10.1109/tcsi.2012.2220453 fatcat:nweo3bvarjcyvjapyaaaztx3im

Deep-Sea: A Reconfigurable Accelerator for Classic CNN

Hao Xiong, Kelin Sun, Bing Zhang, Jingchuan Yang, Huiping Xu
2022 Wireless Communications and Mobile Computing  
low-power all pipelined CNN hardware acceleration architecture is proposed to cope with the continuously updated CNN algorithm and accelerate in hardware platforms with different resource constraints.  ...  To meet the changing real-time edge engineering application requirements of CNN, aiming at the lack of universality and flexibility of CNN hardware acceleration architecture based on ARM+FPGA, a general  ...  supported by the National Key Research and Development Plan of China (Y820043001): Research on deep-sea video acquisition, transmission, and processing technology, system integration and demonstration applications  ... 
doi:10.1155/2022/4726652 doaj:56aafbda8c344dc3bf376daa00cfec29 fatcat:m5zukuy6fjcnbidgm5aewxpndi

Advanced Photonic and Electronic Systems WILGA 2017

Ryszard S. Romaniuk
2017 International Journal of Electronics and Telecommunications  
WILGA 2017 works were published in Proc. SPIE vol.10445.  ...  WILGA annual symposium on advanced photonic and electronic systems has been organized by young scientist for young scientists since two decades.  ...  Testing system consists of tuneable 1550 nm laser, MZ modulator with sampling input at 10 Gbps, SMF, EDFA band pass filter, photodetector, splitter with electrical delay by ¼, ½ and 1 bit, and output phase  ... 
doi:10.1515/eletel-2017-0060 fatcat:uaiab4wmcjb33ao32d7q4tcucq

A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications

Andreas Engel, Andreas Koch, Thomas Siebel
2015 2015 IEEE 40th Local Computer Networks Conference Workshops (LCN Workshops)  
The Hardware-Accelerated Low Power Mote (HaLoMote) is proposed and evaluated in this thesis to address the requirements of compute-intensive WSN applications.  ...  Low-power sleep periods can thus be scheduled within every sampling cycle, even for sampling rates of hundreds of hertz.  ...  This allows for a fine-grained trade-off between encoder complexity and compression ratio.  ... 
doi:10.1109/lcnw.2015.7365908 dblp:conf/lcn/EngelKS15 fatcat:cugvo6duqzgw3lwutiowjjda7m

3D ICS with Optical Interconnections [chapter]

Edward G., Sergey V., Mike B.
2012 Optical Communication  
and inter-processor connections in order to attain high throughput and low power consumption [1] [2] [3] [4] .  ...  After a certain fixed delay, memory cells of the second layer set new states for modulators on their outputs.  ... 
doi:10.5772/47872 fatcat:3o2za6hkgrhxdop2xmacu3tu2y

Fast Functional Imaging of Single Neurons Using Random-Access Multiphoton (RAMP) Microscopy

Vijay Iyer, Tycho M. Hoogland, Peter Saggau
2006 Journal of Neurophysiology  
RAMP microscopy thus comprises a versatile tool for investigating correlations of dendritic structure and function with significantly enhanced experimental throughput.  ...  structures are generally sparse, activity located throughout various compartments, including thin dendritic branches and spines, can be mapped at high frame rates while maintaining the signal-to-noise ratio  ...  Custom software for system manages digital input/output (DIO) and A/D (A/D) boards that interface to the DDS and PMT detection circuitry, respectively.  ... 
doi:10.1152/jn.00865.2005 pmid:16221746 fatcat:35ly4r33mbep3pyquyga2x2yjq

2019 Index IEEE Journal of Solid-State Circuits Vol. 54

2019 IEEE Journal of Solid-State Circuits  
., +, JSSC June 2019 1541-1552 A Harmonic-Selective Multi-Band Wireless Receiver With Digital Har- monic Rejection Calibration.  ...  ., +, JSSC Jan. 2019 18-28 A Low-Noise Fractional-N Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications.  ... 
doi:10.1109/jssc.2019.2956675 fatcat:laiuae7dtragjijttgfatsldmu

Models of computation and languages for embedded system design

A. Jantsch, I. Sander
2005 IEE Proceedings - Computers and digital Techniques  
Models of computation (MoC) are reviewed and organised with respect to the time abstraction they use. Continuous time, discrete time, synchronous and untimed MoCs are distinguished.  ...  Consequently, it is argued that different MoCs are necessary for the various tasks and phases in the design of an embedded system.  ...  Esterel has been designed for synchronous=reactive systems, where a program typically waits for inputs, computes something and emits outputs. Modules communicate with each other via events.  ... 
doi:10.1049/ip-cdt:20045098 fatcat:j6jhhgudbfatvcreknt4rwbkri

D3.1 Selection of metro node architectures and optical technology options

Andrew Lord, Anna Chiadò Piat, Alessandro Percelsi, Marco Quagliotti, Emilio Riccardi, Michela Svaluto Moreolo, Josep M. Fabrega, Laia Nadal, F. Javier Vilchez, Neelakandan Manihatty Bojan, Shuangyi Yan, Reza Nejabati (+30 others)
2018 Zenodo  
The design guidelines and specifications for the technical implementations to be undertaken in WP4 and WP5 are reported, together with a complete outline of the activities undertaken in WP3 during the  ...  D3.1 reports details of the Metro Node and Optical Network Elements architectures together with the relevant design guidelines for the access-metro and metro-core edge nodes, as well as the WDM transport  ...  We define the clipping ratio as the ratio between the input signal standard deviation and the maximum DAC output amplitude.  ... 
doi:10.5281/zenodo.2586697 fatcat:vhgxhkevhvbrzmbw5do6by2m5i

2021 Index IEEE Transactions on Microwave Theory and Techniques Vol. 69

2021 IEEE transactions on microwave theory and techniques  
The Author Index contains the primary entry for each item, listed under the first author's name.  ...  -that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021.  ...  A Four-Way Nested Digital Doherty Power Amplifier for Low-Power Applications.  ... 
doi:10.1109/tmtt.2022.3156771 fatcat:7iov55dzdnbprgd42epirpfaia
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