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Constant Power Consumption Design of Novel Differential Logic Gate for Immunity against Differential Power Analysis
2018
IET Circuits, Devices & Systems
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This study proposes a novel DPA immune design of basic gates, which show the dense distribution of autocorrelation and strong salience strength around 60%. ...
Differential power analysis (DPA) method is frequently used for the non-invasive side-channel attack to hack into the system. ...
Acknowledgment The authors thank the Department of Science and Technology, Govt. of India for their continuous support towards research activities at BITS Pilani institute. ...
doi:10.1049/iet-cds.2018.5093
fatcat:gdohrefeyrfptnm24wvt7t32tm
1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks
2015
2015 Symposium on VLSI Circuits (VLSI Circuits)
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A novel charge-recovery logic family, called Bridge Boost Logic (BBL), is introduced in this design to achieve switching-independent energy dissipation for an intrinsic high resistance against Differential ...
Another effective approach uses gates designed with nearly constant power consumption to diminish the impact of switching activity on the power trace, but these designs incur high performance and power ...
Fig. 1 : 1 (a) Cascade of BBL gates, (b) Schematic of a BBL gate, Fig. 2: Power clock generation and distribution. (c) Simulation operating waveforms. ...
doi:10.1109/vlsic.2015.7231274
dblp:conf/vlsic/LuZP15
fatcat:jor6wa6zwndmnidu2y5pgx3i2a
Charge balancing symmetric pre-resolve adiabatic logic against power analysis attacks
2019
IET Information Security
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Security of the proposed logic against the side channel power analysis attack is demonstrated by performing the correlation power analysis attacks as applicable for the SPICE simulations. ...
Energy deviation for the different input transitions of the individual logic gates, namely, buffer/NOT, AND/NAND and XOR/XNOR is found to be very minimal and it validates the immunity of the proposed logic ...
The main objective in this work is the design of a novel, energy efficient, low power and power analysis robust adiabatic logic style suited to lightweight smart devices. ...
doi:10.1049/iet-ifs.2018.5136
fatcat:3qyjmnqnnbfhhmq3uwhhifdzua
A Novel circuit of SRAM Cell Against Single-Event Multiple Effects for 45nm Technology
2016
International Journal of Computer Applications
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Therefore, designing a reliable novel SRAM cell is an important challenge against SEU. In this paper, the proposed SRAM cell that provides a better features than their recent proposed SRAM cells. ...
The process corner analysis displays the comparison of power and delay of the proposed and existing SRAM cells. It shows that the proposed memory cell consumes less power than previous memory cells. ...
CONCLUSION Previous radiation hardened SRAM cells requires an increase of power consumption and write delay. This paper has given a novel immune SRAM cell. ...
doi:10.5120/ijca2016911429
fatcat:z5zpwrelvfgjpe6zjdwqxdc6oe
Overview of Dual rail with Precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors
2009
2009 3rd International Conference on Signals, Circuits and Systems (SCS)
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This is for instance the case of the Differential Power Analysis (DPA) or the Correlation Power Analysis (CPA). ...
The Masking method allows the designer to get a power consumption which has a constant mean and a variance given by a random variable. ...
Full Custom Optimizations In 2002, Kris Tiri introduces the "Sense Amplifier Based Logic" (SABL) logic style [24] , [25] , which aim is to make power consumption independent of both the logic values ...
doi:10.1109/icscs.2009.5412599
fatcat:hno7nnzwr5a2bizcvioor3aad4
On circuit techniques to improve noise immunity of CMOS dynamic logic
2004
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance ...
Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. ...
We will explain this in detail in Section IV and show a novel class of keeper design techniques that increases gate noise immunity against both internal and external noises with minimal contention. ...
doi:10.1109/tvlsi.2004.833668
fatcat:wbbeuwoyqja45alzzbhst7bbqq
Asynchronous balanced gates tolerant to interconnect variability
2008
2008 IEEE International Symposium on Circuits and Systems
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We present a novel asynchronous dual-rail gate design which is power balanced and capable of tolerating interconnect variability. ...
Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. ...
A promising countermeasure against these attacks has been based on gate-level power balanced designs. ...
doi:10.1109/iscas.2008.4542136
dblp:conf/iscas/KulikowskiVWTK08
fatcat:drhbatfbtngllm2jocyuyt6tou
Power balanced circuits for leakage-power-attacks resilient design
2015
2015 Science and Information Conference (SAI)
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The use power-balanced (m-of-n) logic is a promising solution that provides an answer to this problem, such circuits are designed to consume constant amount of power regardless of data being processed. ...
The continuous rise of static power consumption in modern CMOS technologies has led to the creation of a novel class of security attacks on cryptographic systems. ...
This work will prove for the first time that the use (m-of-n) logic style to design cryptographic system can be an effective countermeasure against the newly developed leakage-based power analysis. ...
doi:10.1109/sai.2015.7237294
fatcat:os3nnlgwlnfy3cxeiktprlc53q
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems
2010
Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10
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It also emits less noise and has flatter power peaks therefore leaks less information against side-channel attacks such as differential power/noise analysis. ...
In this work, a novel asynchronous combinational S-Box (substitution box) design for AES (Advanced Encryption Standard) cryptosystems is proposed and validated. ...
The benefit of dual-rail logic is that the constant power consumption can be achieved since the signals are implemented by two complementary wires. ...
doi:10.1145/1785481.1785587
dblp:conf/glvlsi/WuKC10
fatcat:55vxepve4jhmxded2bm5nfkj7y
Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem
2021
Journal of Low Power Electronics and Applications
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In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. ...
We design and validate the ECC processor using Xilinx ISE 14.7 and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA). ...
Differential side-channel analysis attacks: Differential side-channel analysis attacks (DPA, short for differential power analysis, and DEMA, short for differential electromagnetic analysis) pry out secret ...
doi:10.3390/jlpea11040043
fatcat:witvcqbufjfrfellgkebmjgdqm
Power Side Channels in Security ICs: Hardware Countermeasures
[article]
2016
arXiv
pre-print
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This paper reviews foundational power analysis attack techniques and examines a variety of hardware design mitigations. ...
Power side-channel attacks are a very effective cryptanalysis technique that can infer secret keys of security ICs by monitoring the power consumption. ...
It employs monotonic gates to avoid glitches, and it fights against leakage of mask bits and early propagation using a novel activity image analysis for combinational data paths. ...
arXiv:1605.00681v1
fatcat:lwx5jvoh5nh2ziyr3ibuuctxdq
Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic
2013
International Journal of Modeling and Optimization
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The full custom design of the layout has been designed in cadence virtuoso IC6.1 with the chip size of 172×155 m 2 , and the post-layout cyclical power consumption of 14pJ at 12.5MHz using 0.18μm CMOS ...
The thoroughly investigation results define that our proposed logic improve energy reduction and the circuit immunity to side-channel attack in the low frequency application, whereas, the TDPL shows the ...
measure the parameters of NED and NSD which means the ability of the logic resistance against power analysis attack. ...
doi:10.7763/ijmo.2013.v3.292
fatcat:tgfv2kkbl5hilpdjvqnyvq3jga
Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
2012
International Journal of VLSI Design & Communication Systems
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This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. ...
The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. ...
Immunity to Noise Comparison Analysis To test the immunity of the circuits to the ambient temperature noise and variations, the designs are simulated in a vast range of temperature range from 0 o C to ...
doi:10.5121/vlsic.2012.3219
fatcat:qrdrfjuhfba2tmveyt3kkvjmzq
Repeater and current-sensing hybrid circuits for on-chip interconnects
2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03
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Static power consumption inherited from differential current-sensing is the biggest drawback of the hybrid circuits. ...
Comparison in terms of delay, power and area is drawn between various versions of the hybrid circuit with delay-optimal repeater insertion and differential current sensing in order to derive at the best ...
Higher power consumption in hybrids is mainly due to the static power consumption in current-sensing part of the circuit. ...
doi:10.1145/764867.764878
fatcat:6p6tsi6a7rfhlnndoidxs25f7q
Repeater and current-sensing hybrid circuits for on-chip interconnects
2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03
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Static power consumption inherited from differential current-sensing is the biggest drawback of the hybrid circuits. ...
Comparison in terms of delay, power and area is drawn between various versions of the hybrid circuit with delay-optimal repeater insertion and differential current sensing in order to derive at the best ...
Higher power consumption in hybrids is mainly due to the static power consumption in current-sensing part of the circuit. ...
doi:10.1145/764808.764878
dblp:conf/glvlsi/MaheshwariB03
fatcat:ta6qv6dbsbconf4jqvqps3ojzq
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