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Erasing Core Boundaries for Robust and Configurable Performance
2010
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
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Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. ...
Further, as a manifestation of this vision, the paper provides details of a unified performance-reliability solution that can assemble variable-width processors from a network of (potentially broken) pipeline ...
Single-thread performance Configurable performance in CG relies on its ability to accelerate single-thread performance by conjoining in-order pipelines. ...
doi:10.1109/micro.2010.30
dblp:conf/micro/GuptaFAM10
fatcat:lc3gdrfzkvcnbmpiexqbwnooay
Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems
2009
2009 IEEE/IFIP International Conference on Dependable Systems & Networks
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Our second technique (STEM) adds timing error detection capability to guarantee reliable execution in aggressively clocked designs that enhance system performance by operating beyond worst-case clock frequency ...
Timing annotated gate level simulations, using 45nm libraries, of a pipelined adder-multiplier and DLX processor show that both our techniques achieve near 100% fault coverage. ...
CPipe architecture enables reliable overclocking and enhances system reliability through core replication and conjoining them. ...
doi:10.1109/dsn.2009.5270340
dblp:conf/dsn/AvirneniSS09
fatcat:pqo6ov6cm5dfde73zzcqovuh5m
Dynamically configurable shared CMP helper engines for improved performance
2005
SIGARCH Computer Architecture News
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Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. ...
In a multicore environment, our intelligent and flexible sharing of helper engines, provides an average 24% speedup over static sharing in conjoined cores. ...
He then describes how surrounding this simple core pipeline with helper engines that perform speculative tasks off the critical path results in enhanced overall performance. ...
doi:10.1145/1105734.1105744
fatcat:6yazv4fkbzckfcyqlnfa65h2de
High-Performance Energy-Efficient Multicore Embedded Computing
2012
IEEE Transactions on Parallel and Distributed Systems
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This paper outlines typical requirements of embedded applications and discusses state-of-the-art hardware/software high-performance energy-efficient embedded computing (HPEEC) techniques that help meeting ...
Finally, we present design challenges and future research directions for HPEEC system development. ...
ACKNOWLEDGMENTS This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) and the US National Science Foundation (NSF) (CNS-0953447 and CNS-0905308). ...
doi:10.1109/tpds.2011.214
fatcat:vagqmojdsjevvc2u2ewqrcjjpq
Improving the performance and power efficiency of shared helpers in CMPs
2006
Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06
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Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. ...
In a multicore environment, our intelligent and flexible sharing of helper provides an average 24% speedup compared to static sharing in conjoined cores. ...
He then describes how surrounding this simple core pipeline with helpers that perform speculative tasks off the critical path results in enhanced overall performance. ...
doi:10.1145/1176760.1176802
dblp:conf/cases/ShayestehRJSS06
fatcat:duoakcfkgjgotl6jtq3rxp23bq
Plug-in Electric Vehicle to Cloud Data Analytics for Charging Management
2017
International Journal of Engineering and Technology
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architecture destined to have a reliable and real time operation of engaged utilities [4] . ...
Conceptually, xEVs integrate the electrical networks with so called data and communication infrastructures through smart metering and sensing utilities [2] . ...
The overall performance is tuned up by involving human factor in the loop to interpret and utilize the output from the DF pipeline. ...
doi:10.21817/ijet/2017/v9i3/170903s056
fatcat:6c3konyo6rb5rjofa54246smsq
Pre-Trained Models: Past, Present and Future
[article]
2021
arXiv
pre-print
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Finally, we discuss a series of open problems and research directions of PTMs, and hope our view can inspire and advance the future study of PTMs. ...
, improving computational efficiency, and conducting interpretation and theoretical analysis. ...
of neural networks and hardware configuration (Ben-Nun and Hoefler, 2019). ...
arXiv:2106.07139v3
fatcat:kn6gk2bg4jecndvlhhvq32x724
Rigorous system design
2014
Proceedings of the 2014 ACM symposium on Principles of distributed computing - PODC '14
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The paper has benefited from constructive comments and criticism by Peter Denning and two anonymous reviewers. ...
Acknowledgments The presented vision presented amply relies on theory, and experimental results developed by the BIP team. ...
The resulting hardware platforms for such systems are excessively over-dimensioned. Another principle from critical systems engineering consists in using massive redundancy to enhance reliability. ...
doi:10.1145/2611462.2611517
dblp:conf/podc/Sifakis13
fatcat:dmj4scewsrhfvf3rxbtqpeacxa
Analytical Review of Cybersecurity for Embedded Systems
2020
IEEE Access
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(12) the players (manufacturers, legislators, operators, and users). ...
The study provides a clear landscape of CSES and, therefore, could help to find better comprehensive solutions for CSES. ...
[27] presented a hardware-enhanced protection method to maintain the confidentiality and integrity of data by using an AES stream encryption engine. ...
doi:10.1109/access.2020.3045972
fatcat:vhl6dvaxezaebmyjszptej763y
Delay Insensitive Ternary CMOS Logic for Secure Hardware
2015
Journal of Low Power Electronics and Applications
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wire per bit, three voltage signaling and logic scheme. ...
DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. ...
Smith, and Jia Di conceived and designed the experiments; Ravi S. P. Nair performed the experiments; Ravi S. P. Nair, Scott C. Smith, and Jia Di analyzed the data; Jia Di and Scott C. ...
doi:10.3390/jlpea5030183
fatcat:is7pzrncsfgoxa6nacqgju4yeq
System Level Analysis for Achieving Thermal Balance and Lifetime Reliability in Reliably Overclocked Systems
unpublished
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We, then, evaluate the effects of thermal throttling, a technique that clamps the on-chip temperature below a predefined value, on system performance and reliability. ...
We analyze how reliable overclocking impacts the on-chip temperature of microprocessors, and evaluate the effects of overheating, due to reliable dynamic overclocking mechanisms, on the lifetime reliability ...
ACKNOWLEDGMENT The research reported in this paper is partially supported by NSF grant number 0311061 and the Jerry R. Junkins Endowment at Iowa State University. ...
fatcat:zbwwkddsgbcqzoo5oxbzgkzs4u
COST IC1404 WG1 Deliverable WG1.2: Framework to Relate / Combine Modeling Languages and Techniques
2019
Zenodo
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Ontological foundation for a framework to Relate / Combine Modeling Languages and Techniques. ...
Subclass of • Sustainability (see section 3.4.3.21)
Reliability Reliability refers to the degree of correctness which a system provides to perform its function. ...
Continuous monitoring and testing of the infrastructure can be performed through those mechanisms. The outcome of monitoring and testing facilities help finding which units need to be repaired. ...
doi:10.5281/zenodo.2538795
fatcat:ox2slzxzdbcrjha2xeoz75a7vy
Systems Security Engineering
2011
IEEE Security and Privacy
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the data needed, and completing and reviewing the collection of information. ...
Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining ...
the newly conjoined system of systems. ...
doi:10.1109/msp.2011.41
fatcat:luk7ndqzvfgexg2wrnwsji5rci
COST IC1404 WG1 Deliverable WG1.2: Framework to Relate / Combine Modeling Languages and Techniques
2019
Zenodo
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The file type is application/pdf.
Ontological foundation for a framework to Relate / Combine Modeling Languages and Techniques. ...
Subclass of • Sustainability (see section 3.4.3.21)
Reliability Reliability refers to the degree of correctness which a system provides to perform its function. ...
Continuous monitoring and testing of the infrastructure can be performed through those mechanisms. The outcome of monitoring and testing facilities help finding which units need to be repaired. ...
doi:10.5281/zenodo.2527577
fatcat:qsugbjnclbe4hnz46sunlqvj5a
Integrated Application of Compositional and Behavioural Safety Analysis
[chapter]
2011
Advances in Intelligent and Soft Computing
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In a more detailed design, redundancy can be implemented in the hardware, software, or information domain. ...
A function is performed by one or more system elements composed of hardware, software, firmware, people, and procedures to achieve system operations. ...
doi:10.1007/978-3-642-21393-9_14
fatcat:hxaga5jvybhf7dnddr7s5hibo4
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