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Arithmetic pattern generators for built-in self-test

A.P. Stroele
Proceedings International Conference on Computer Design. VLSI in Computers and Processors  
In this paper guidelines for the design of arithmetic pattern generators are developed.  ...  Experimental results show that the generated patterns achieve similar fault coverage as pseudo-random sequences and require about the same test length.  ...  as shown in figure 1. pattern generator Figure 1 ; General configuration of a pattern generator This structure generates a new pattern in every clock cycle and applies it to the circuit under test (CUT  ... 
doi:10.1109/iccd.1996.563545 dblp:conf/iccd/Stroele96 fatcat:hbud7jgwdvd6hjq5lhcpyvqgtu

An industrial view of electronic design automation

D. MacMillen, R. Camposano, D. Hill, T.W. Williams
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation.  ...  The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa.  ...  The modern verification languages Vera, from Systems Science, now part of Synopsys, and Specman, from Verisity, appeared in response, developed from the start with a focus on functional verification.  ... 
doi:10.1109/43.898825 fatcat:hhk7zrepyfcyxgizvotqck7cei

Considering testability during high-level design

S. Dey, A. Raghunathan, R.K. Roy
Proceedings of 1998 Asia and South Pacific Design Automation Conference  
This paper presents an overview of high level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits.  ...  The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targetting ATPG (full and partial scan) and BIST methodologies, and techniques to  ...  Using Arithmetic Units as Test Generators and Compactors Instead of using special BIST hardware like TPGRs and SRs, functional units can be used to perform test pattern generation and test response compaction  ... 
doi:10.1109/aspdac.1998.669447 dblp:conf/aspdac/DeyRR98 fatcat:xdnbnccq75gedi7jx53rx4cuq4

Online test vector insertion - a concurrent built-in self-testing (CBIST) approach for asynchronous logic

Jürgen Maier, Andreas Steininger
The units responsible for merging and splitting had to be implemented from scratch due to missing references in literature, both for the bundled data and completion detection communication style and in  ...  For that purpose the rather unproductive NULL-phase of a 4-phase communication protocol is replaced by dedicated TEST values, which are generated and analysed on chip.  ...  For that purpose automated test pattern generators (ATPG) have been proposed (e.g. in [33, 42] ) that analyse a circuit and generate a fitting test set.  ... 
doi:10.34726/hss.2014.25295 fatcat:bqedultj3fedjhho43s7hiqqsy