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Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips

Jeffrey McDaniel, Brendon Parker, Philip Brisk
2014 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)  
Microfluidic large-scale integration (mLSI) chips comprise hundreds or thousands of microvalves integrated into a chemically inert elastomeric substrate.  ...  To enhance design automation, a routability-oriented placement algorithm based on simulated annealing is introduced.  ...  INTRODUCTION Microfluidic large-scale integration (mLSI) chips automate and miniaturize high throughput biochemical laboratory procedures through a network of microvalves controlled by external pneumatic  ... 
doi:10.1109/vlsi-soc.2014.7004170 dblp:conf/vlsi/McDanielPB14 fatcat:cwvfxdiexbbrzgazpfvq6ugk4q

Table of Contents

2021 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)  
on Very Large Scale Integration (VLSI-SoC) | 978-1-6654-2614-5/21/$31.00 ©2021 IEEE | DOI: 10.1109/VLSI-SoC53125.2021.9607014 On 1 Metamorphic Testing for Processor Verification: A RISC-V Case Study at  ...  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Akshay Balaji and Sneh Saurabh 2021 IFIP/IEEE 29th International Conference  ... 
doi:10.1109/vlsi-soc53125.2021.9607014 fatcat:tvd5rehezzbsjpkfdxdryj74tq

VLSI-SoC 2021 Cover Page

2021 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)  
session management through virtual conference hosting platforms.  ...  Various active roles were played by different committee members, from inviting excellent special session papers, ensuring high quality PhD forum submissions, managing conference accounts to the final conference  ...  Message from the Program Co-Chairs We are pleased to present the technical program for the 29th IFIP/IEEE International Conference on Very Large Scale Integration 2021 (VLSI-SoC 2021).  ... 
doi:10.1109/vlsi-soc53125.2021.9607007 fatcat:a6dyjqad2ffn3abcicafyqel3i

Emerging technologies and nanoscale computing fabrics

Ian O'Connor
2009 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)  
on very flexible hardware.  ...  integration of new devices into many-core computing platforms, through the implementation of a vert ical and integrated research approach.  ... 
doi:10.1109/vlsisoc.2009.6041320 fatcat:xcotcekxwfho5abh6ydylfc564

Hardware Trojans in Reconfigurable Computing

Qazi Arbab Ahmed
2021 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)  
A special thanks goes to my colleague cum mentor Tobias Wiersema who has been there all the time for scientific discussions in a very professional way and also his help regarding social matters in Germany  ...  Most of the work on hardware Trojans has been focused on fixedfunction circuits, i.e., application-specific integrated circuits (ASICs), while very little effort has been shown towards dynamically reconfigurable  ...  FPGAs have been a large driving force for reconfigurable computing for many years.  ... 
doi:10.1109/vlsi-soc53125.2021.9606974 fatcat:udwjtbtd4vdsljv64s3qgsjeey

Parallelized radix-2 scalable Montgomery multiplier

Nan Jiang, David Harris
2007 2007 IFIP International Conference on Very Large Scale Integration  
On a Virtex-II FPGA, this design can perform 1024-bit modular exponentiation in 6.3 ms using 6006 lookup tables, a 17% speed improvement over the previously fastest scalable radix-2 Montgomery multiplier  ...  The latency of a kernel cycle depends on e and p. Case I corresponds to a large number of PE cycles, e, relative to the number of processing elements, p.  ...  However, the hardware efficiency comes at the cost of large number of iterations through the kernel.  ... 
doi:10.1109/vlsisoc.2007.4402488 dblp:conf/vlsi/JiangH07 fatcat:g3vhf3rnarb5lg6esfrahn6k7q

Decimal engine for energy-efficient multicore processors

Alberto Nannarelli
2014 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)  
In the dark silicon era, where not all the circuits on the die can be powered simultaneously, we propose a hybrid BFP/DFP engine to perform BFP division and DFP addition, multiplication and division.  ...  With technology scaling the number of cores, or functional units, increases at each generation, but the power necessary to power the whole chip has increased to a point that it is no longer possible to  ...  Moreover, because the hardware for DFP division is very similar to that of BFP division, we can combine BFP-div in the UniPro as well, and further reduce latency and power with respect to the FMA implementation  ... 
doi:10.1109/vlsi-soc.2014.7004176 dblp:conf/vlsi/Nannarelli14 fatcat:kvg75ibcg5ar3aezyuaoxqolme

Scaling of advanced floating body Z-RAM storage cells: A modeling approach

Viktor Sverdlov, Siegfried Selberherr
2009 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)  
The programming window is appropriately large in voltage as well as in current. We further extend our study to a Z-RAM cell based on an ultra-scaled double-gate MOSFET with 12.5nm gate length.  ...  We demonstrate that the cell preserves its functionality by providing a wide voltage operating window with large current differences.  ...  CONCLUSION We have shown that a Z-RAM cell built on a scaled doublegate MOSFET preserves its functionality by providing a wide voltage operating window with large current differences.  ... 
doi:10.1109/vlsisoc.2009.6041352 fatcat:trwpxaetafbynmv6y5zygbt3iu

Dynamic gates with hysteresis and configurable noise tolerance

Krishna Santhanam, Kenneth S. Stevens
2007 2007 IFIP International Conference on Very Large Scale Integration  
This results in a very efficient gate.  ...  Figure 7 shows the DC analysis of a 2-input NAND gate as the CDL keeper gate scales. For large keepers a substantial hysteresis differential is created.  ... 
doi:10.1109/vlsisoc.2007.4402495 dblp:conf/vlsi/SanthanamS07 fatcat:qxszacbo3veermcofmltlmrhhi

On the accuracy of Monte Carlo yield estimators

Alp Arslan Bayrakci
2013 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)  
However, the MC methods can have very different levels of accuracy depending on the model used beneath the method.  ...  In this paper, we build and compare three different MC yield estimators to see the effect of the models used beneath the estimator on the accuracy.  ...  Proceedings of 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) 2) Block Level Monte Carlo Based on Linear Models (BL-MC-Lin): This MC estimator computes gate delays  ... 
doi:10.1109/vlsi-soc.2013.6673247 dblp:conf/vlsi/Bayrakci13 fatcat:x3aiojyxijdq3pxhjrtxfhzndm

Clocked and asynchronous FIFO characterization and comparison

HoSuk Han, Kenneth S. Stevens
2009 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)  
Heterogeneous blocks, IP reuse, network-on-chip interconnect, and multi-frequency design are becoming more prevalent in integrated circuit design.  ...  However, designs with large latencies restrict throughput across a large range of occupancies. The clocked linear FIFO has a very high latency.  ...  The simulation results are evaluated and first order models developed for capacity, throughput, energy scaling, and performance values.  ... 
doi:10.1109/vlsisoc.2009.6041338 fatcat:wwze7boapbejhemso5zr2bt54q

Fine grain word length optimization for dynamic precision scaling in DSP systems

Seogoo Lee, Andreas Gerstlauer
2013 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)  
Dynamic precision scaling is a promising technique to reduce power consumption in Digital Signal Processing (DSP) systems.  ...  One of the obstacles of such techniques is that they require an optimization of word lengths for all intermediate values at all possible operation points.  ...  Hence, on average, large power savings can be expected. Finally, Figure 6 and Figure 7 plot the results of performance simulations.  ... 
doi:10.1109/vlsi-soc.2013.6673287 dblp:conf/vlsi/LeeG13 fatcat:ti4b3iduqbguzfq52cwuki2agm

Power-aware SoC test optimization through dynamic voltage and frequency scaling

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal
2013 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)  
Reducing test cost by minimizing the overall test time remains one of the main goals of System-on-Chip (SoC) testing.  ...  Dynamic voltage and frequency scaling (DVFS) techniques have been used in the past to optimize energy efficiency in SoCs.  ...  INTRODUCTION A system-on-chip (SoC) may contain an entire system integrated onto a single chip. Such an SoC is often implemented by embedding reusable blocks called cores.  ... 
doi:10.1109/vlsi-soc.2013.6673258 dblp:conf/vlsi/SheshadriAA13 fatcat:o2u3l54ilbebtnonfln25asl4e

Fast thermal-aware floorplanning using white-space optimization

Sheldon Logan, Matthew R. Guthaus
2009 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)  
In this paper we present a method to help reduce the temperature of chips at the floorplan design level by adjusting block utilizations based on the available whitespace in a floorplan.  ...  INTRODUCTION High on-chip temperatures have quickly become one of the major concerns for modern integrated circuit designers.  ...  Extreme power densities due to the aggressive scaling of transistor sizes have resulted in large peak temperatures and drastic temperature gradients.  ... 
doi:10.1109/vlsisoc.2009.6041332 fatcat:wovagsiqvrh75kvhxhgmsorqbi

Implementation of core coalition on FPGAs

Kaushik Triyambaka Mysur, Mihai Pricopi, Thomas Marconi, Tulika Mitra
2013 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)  
In this paper, we present the first hardware implementation of a core coalition architecture and synthesize its functional prototype on FPGAs.  ...  Dynamic heterogeneous multi-core architectures take this concept forward by allowing on-demand formation of virtual asymmetric multi-cores through coalition of physically symmetric simple cores and thus  ...  Figure 2 shows the seamless integration of coalition logic into the base pipeline.  ... 
doi:10.1109/vlsi-soc.2013.6673275 dblp:conf/vlsi/MysurPMM13 fatcat:4kn2t2ntsnfmtcmgwaywf6ivyy
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