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Comparative Analysis of Low Power Sequential Elements

T PrabhulingamGoud, Eliyaz Mohammed
2013 International Journal of Computer Applications  
Main constraint for any VLSI system is power, speed and area but power consumption is major hurdle for system performance.  ...  Such as conditional data mapping flip-flop (CDMFF), clocked pair shared flip-flop (CPSFF) and new proposed flip-flop in which dual edge triggered technique is used.  ...  Conditional Data Mapping Flip-Flop: Conditional data mapping flip-flop (CDMFF, Fig.1 When the flip-flop is turning in to the transparency period again, no internal transition exists, and (Q,QB) retain  ... 
doi:10.5120/13955-1919 fatcat:euhh2v6wvfhpxfayabkcybxgya

A Novel Analysis on Low-Power High-Performance Flip-Flops

Akila. M, Sathiskumar.M Sathiskumar.M, Sukanya. T
2014 International Journal of Computer Applications  
The comparative power analysis and performance improvements indicate that the proposed design is suitable for high-performance digital designs where the area and power dissipation is of major concern.  ...  In this paper, several different flip-flop topologies are analyzed and an area, power efficient flip-flop design is proposed.  ...  INTRODUCTION Over the past decade, power consumption of VLSI chips has been continuously increasing. The need for low-power design is becoming a vital parameter in high-performance digital systems.  ... 
doi:10.5120/15807-4558 fatcat:thjyhjz3hfehzmtoiv2izyw3fe

A high performance D-flip flop design with low power clocking system using MTCMOS technique

P. Dobriyal, K. Sharma, M. Sethi, G. Sharma
2013 2013 3rd IEEE International Advance Computing Conference (IACC)  
Among those techniques clocked pair shared flip-flop (CPSFF) consume least power than conditional data mapping flip flop (CDMFF), conditional discharge flip flop (CDFF) and conventional double edge triggered  ...  In this paper, various techniques for implementing flip-flops with low power clocking system are analyzed.  ...  Fig. 1: conventional double edge triggered flip-flop (DEFF), conditional discharge flip-flop (CDFF), conditional data mapping flip-flop (CDMFF) and clocked pair shared flip-flop (CPSFF).  ... 
doi:10.1109/iadcc.2013.6514453 fatcat:m4qsseqdb5avzh3xcaei333qhe

D Flip Flop with Low Power Clocking System by using MTCMOS and Slumber Keeper Technique

Anusha Kondam
2017 International Journal for Research in Applied Science and Engineering Technology  
of power than conditional statistics mapping flip flop (cdsff),conditional expulsion flip flop (ceff) and conservative twin edge triggered flip-flop (teff). we put forward a new (cpcff-mt) with slumbery  ...  of techniques to implementing flip-flops with low power clocking structure is analyzed. among those different techniques clocked pair communal flip-flop using mtcmos(cpcff-mt) consume smallest amount  ...  as shown in the Fig. 1: conservative twin edge triggered flip-flop (TEFF), conditional expulsion flip-flop (CEFF), conditional data mapping flip-flop(CDSFF) and clocked pair shared flip-flop (CPCSF).  ... 
doi:10.22214/ijraset.2017.4106 fatcat:l3hjs5kbi5fatmpjmrz3nvrj4y

An explicit-pulsed double-edge triggered JK flip-flop

Yanyun Dai, Jizhong Shen
2009 2009 International Conference on Wireless Communications & Signal Processing  
This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance.  ...  The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops.  ...  Downey, 2009. lowest power consumption and is therefore suitable for "Low Power Clocked Pseudo NMOS Flip Flop for use in high performance and low power environments.  ... 
doi:10.1109/wcsp.2009.5371580 fatcat:ktwjkqnegnetflsxbt5mgszrti

Design A High Speed Spin-Torque Transfer Magnetic Tunnel Junction (Stt-Mtj) NonVolatile Flip-Flops Based On Memory

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
By using STT-MTJs based flip flop, high energy consumption will be obtained and there will be backup of the system. In CMOS the flip flop will used standard magnetic MRAM technology.  ...  The main intent of magnetic tunnel junctions is to store the data. The proposed non volatile flip flop will determine the delay and energy.  ...  D.conditional data mapping flip-flop (cdmff): In this seven timed transistors are used to map the flip flop in effective way. In this detection of low power depends on the swing condition.  ... 
doi:10.35940/ijitee.k2545.0981119 fatcat:b3jfpxavlnfb3hkghuj3qwpixe

Power Optimization Using Dual Dynamic Node Pulsed Hybrid Flip-Flop Based on Footed Logic
english

Indumathi.M, A.Je ena Thankachan
2015 International Journal of Innovative Research in Computer and Communication Engineering  
Designing a new dual dynamic node hybrid flip-flop (DDFF) and low power 4/5 Counter was based on DDFF using FOOTED logic.  ...  The DDFF offers a power reduction of up to 62% and 48% compared to the conventional flipflops like Power PC 603 flip-flop and semi dynamic flip-flop.  ...  Conditional Data Mapping Flip Flop(CDMFF) A new family of low power and high-performance flip flops, namely conditional data mapping flip flops (CDMFFs), which reduce their dynamic power by mapping their  ... 
doi:10.15680/ijircce.2015.0305009 fatcat:x6ktdylx4bbs5awmcyutbc6vtm

Edge-Triggered Pulsed Sequential Elements with SoC Applications

Ch. Lavanya, N. Gopichand, L. Srinivas
2016 International journal of computer and communication technology  
In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.  ...  In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors.  ...  ACKNOWLEDGEMENTS The authors would like to thank the anonymous reviewers for their comments which were very helpful in improving the quality and presentation of this paper.  ... 
doi:10.47893/ijcct.2016.1353 fatcat:vpmp3scbnjamjlauwgd33oiwfy

Design of Sequential Elements for Low Power Clocking System

Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, Zhongfeng Wang
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems. Index Terms-Flip-flop, low power.  ...  Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008.  ...  To use low swing clock distribution, the flip-flop should be a low swing flip-flop. For example, low swing double-edge flip-flop (LSDFF) [8] is a low swing flip-flop.  ... 
doi:10.1109/tvlsi.2009.2038705 fatcat:kilj5utsybffjfnptmkivlbdz4

Design of Hybrid Pulsed FlipFlop Featuring Embedded logic

N. Karthika, S. Jayanthy
2014 IOSR Journal of VLSI and Signal processing  
The performance of modern high performance flip-flops are compared with that of HPFF at different data activity.  ...  The performance improvements indicate that the proposed designs are well suited for modern high-performance circuits where power dissipation and area overhead are of major concern.  ...  The flip-flops considered for analysis are PowerPC 603, Hybrid-Latch flip-flop (HLFF), Semi-dynamic flip-flop (SDFF), conditional data mapping flip-flop (CDMFF), Cross charge control flip-flop (XCFF) and  ... 
doi:10.9790/4200-04216874 fatcat:a7rknbmdzjgv3g3kf656bax7u4

EFFICIENT TIMING ELEMENT DESIGN FEATURING LOW POWER VLSI APPLICATIONS

Nagarajan P., Kavitha T., Shiyamala S.
2016 International Journal of Engineering and Technology  
In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered (DDNET) flip flop for Featuring Efficient low power applications.  ...  The performance improvements specify that the proposed Designs are appropriate for modern high-performance designs where power dissipation is of major Concern.  ...  The performances of proposed modern high performance flip-flops architecture are compared with that of dual dynamic node hybrid flip-flop (DDFF) different data activity and power factor.  ... 
doi:10.21817/ijet/2016/v8i4/160804409 fatcat:i3r4wgp3uvd5ng4eticugs52fq

A NEW REDUCED CLOCK POWER FLIP-FLOP FOR FUTURE SOC APPLICATIONS

MOHAMMADRAFI SHAIK, LLAPAVULURI ADITYA ABHILASH, PADALA SRINIVAS
2013 International Journal of Electronics Signals and Systems  
In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D flip flop(CPSFF) here we are checking the working of  ...  CDMFF and the conventional D Flip-flop.  ...  CONVENTIONAL CONDITIONAL DATA MAPPING D FLIP-FLOP Flip-Flops are the basic elements for storing information and they are the fundamental building blocks for all sequential circuits.  ... 
doi:10.47893/ijess.2013.1125 fatcat:ol4zeb56fzb5jgi2vo56wfj2r4

Designing a Novel Power Efficient D- Flip-Flop using Forced Stack Technique

Karna Sharma, Manan Sethi, Paanshul Dobriyal, Geetanjali Sharma
2013 International Journal of Computer Applications  
In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce the power consumed by flip-flops and latches.  ...  In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network.  ...  VARIOUS LOW POWER CLOCKING FLIP-FLOPS There are various genres of D flip-flops and they are categorized as: conditional discharge flip-flop (CDFF), conditional data mapping flip-flop (CDMFF) and clocked  ... 
doi:10.5120/11608-6984 fatcat:7pm7bgp2i5agvptbschh36vwj4

Design and Implementation of Embedded Logic Flip-Flop for Low Power Applications

A. Sudheer, Ajith Ravindran
2015 Procedia Computer Science  
It will be a good component for including in VLSI standard cell library for designing high performance chips for low power applications.  ...  This paper introduces a high performance hybrid flip-flop which can merge logic functions with normal flip-flop operation.  ...  The flip-flops considered for analysis are Hybrid-Latch Flipflop (HLFF) 1 , Semi Dynamic Flip-flop (SDFF) 2 , Conditional Data Mapping Flip-flop (CDMFF) 3, 4, 5 , Cross Charge Control Flip-flop (XCFF)  ... 
doi:10.1016/j.procs.2015.02.057 fatcat:tkdxjbgeqfa2nhre7iq362bhby

Effect of clock gating in conditional pulse enhancement flip-flop for low power applications

Kuruvilla John, Vinod Kumar R. S., Kumar S. S.
2019 Indonesian Journal of Electrical Engineering and Informatics (IJEEI)  
Flip-Flops (FFs) play a fundamental role in digital designs. A clock system consumes above 25% of total system power.  ...  This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. This flipflop architecture is embedded with two key features.  ...  ACKNOWLEDGMENTS The authors would like to thank the Department of Electronics & Communication Engineering of SAINTGITS Engineering College, Kottayam, India, for providing the VLSI research laboratory facility  ... 
doi:10.52549/ijeei.v7i2.1041 fatcat:2ejo4o6bcrh5plxlgfk4j7efhy
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