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Page 3627 of Mathematical Reviews Vol. , Issue 94f
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1994
Mathematical Reviews
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L. (1-MN-E; Minneapolis, MN) Concurrent error detection in sequential circuits using convolutional codes. ...
Summary: “Concurrent error detection schemes in digital sys- tems are often based upon error-detecting codes. ...
1983 Index IEEE Transactions on Computers Vol. C-32
1983
IEEE transactions on computers
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R., T-CMay83497-500 concurrent error detection in multiply and divide arrays. ...
Cyclic coding; Residue coding Error-detection coding code constructions for error control in byte-organized memory systems. ...
doi:10.1109/tc.1983.1676190
fatcat:xsogjoynp5dt7mqu6dy4tiodfq
Rapid Prototyping of Embedded Video Processing Systems in FPGA Devices
[chapter]
2015
Cutting Edge Research in Technologies
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We propose a novel design flow for generating customizable intellectual property (IP) cores used in streaming video processing applications. ...
This design flow is based on domain-specific modules in Python language. Examples of generated cores are presented. ...
The code() method is used to add MyHDL statements into statement code list (C[]). The function code is translated into a set of MyHDL combinational and sequential functions using getcode() method. ...
doi:10.5772/61136
fatcat:6zmk7dt5hrearl3rxmoxqkimyu
A framework for ABFT techniques in the design of fault-tolerant computing systems
2011
EURASIP Journal on Advances in Signal Processing
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Number data processing errors are detected by comparing parity values associated with a convolution code. ...
The ABFT error detection technique relies on the comparison of parity values computed in two ways. ...
In other words, the encoder is a sequential circuit [15, 17, 20] . ...
doi:10.1186/1687-6180-2011-90
fatcat:5musgxx2xzgphhnll33onmsuou
Implementation Analysis of adaptive Viterbi Decoder for High Speed Applications
2011
International Journal of Computer Applications
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Viterbi Algorithm is the optimum-decoding algorithm for convolutional codes and has often been served as a standard technique in digital communication systems for maximum likelihood sequence estimation ...
The designed Adaptive Viterbi Decoder is able to detect and correct up to four errors. The design is optimized with respect to time, area and power and the netlist is generated. ...
Convolutional codes are frequently used to correct errors in noisy channels. ...
doi:10.5120/3797-5232
fatcat:r3y7vlfpfnamziztpstycut5ve
Selective Code Duplication for Soft Error Protection on VLIW Architectures
2021
Electronics
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However, the previous static scheme duplicates instructions just in sequential order. ...
., NOPs) in VLIW architectures. All the instructions cannot be replicated without additional code lines. ...
We estimated the cell area of our VLIW architecture by using the Synopsys Processor Designer [35] to detect soft errors as shown in Table 1 . ...
doi:10.3390/electronics10151835
fatcat:hcllk63htjg5dpp4mrqdoj2e6a
Memory-span concepts and the synthesis of sequential machines in feedback shift-register form
1967
8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
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Convolution Algorithm: Distribution of jobs in a system; Convolution
algorithm for computing G(N); Computing performance using G(N);
Timesharing systems. ...
Image Segmentation Detection of discontinuities, Edge linking and boundary detection, Thresholding, Region-based segmentation, Segmentation by morphological watersheds and the use of motion in segmentation ...
doi:10.1109/focs.1967.19
dblp:conf/focs/Martin67
fatcat:fwn5xjv7mbcsja5xrhcmdo6ipe
Sequential and Parallel Cascaded Convolutional Encryption with Local Propagation: Toward Future Directions in Symmetric Cryptography
2006
Third International Conference on Information Technology: New Generations (ITNG'06)
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In this paper, we propose efficient alternatives based on special classes of globally invertible cascaded convolutional transducers. ...
Worldwide symmetric encryption standards such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and EES (Escrowed Encryption Standard), have been -and some of them still are -extensively used ...
Even though convolutional codes have been primarily designed for error detection and correction, they can be successfully used in related areas such as cryptography, as we will see throughout this presentation ...
doi:10.1109/itng.2006.120
dblp:conf/itng/Trinca06
fatcat:mcfrqi6wtvb5bczk4yzg4etoo4
Repository [advertisement]
1977
Computer
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five different systems using a (12,6) systematic, double error correcting, convolutional encoder and a one-step majority logic feedback decoder. ...
This approximation method has been partially misinterpreted in "The error latency of a fault in a sequential digital circuit." The present comments are mainly concerned with these interpretations. ...
doi:10.1109/c-m.1977.217841
fatcat:4ozrmqss4nevllihids24lhmzm
SEU tolerant device, circuit and processor design
2005
Proceedings. 42nd Design Automation Conference, 2005.
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Methods of systems engineering process and the application and validation of techniques for fault tolerance are discussed as elements in the elimination and mitigation of single event upsets. ...
Cyclic redundancy checks, other cyclic codes, and convolutional coding schemes are used to detect errors in serial data transfer interfaces and storage media; such codes are generally classified as either ...
block codes or convolutional codes. ...
doi:10.1109/dac.2005.193763
fatcat:ich4umqtj5ectpri5r3n6to4nq
SEU tolerant device, circuit and processor design
2005
Proceedings of the 42nd annual conference on Design automation - DAC '05
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Methods of systems engineering process and the application and validation of techniques for fault tolerance are discussed as elements in the elimination and mitigation of single event upsets. ...
Cyclic redundancy checks, other cyclic codes, and convolutional coding schemes are used to detect errors in serial data transfer interfaces and storage media; such codes are generally classified as either ...
block codes or convolutional codes. ...
doi:10.1145/1065579.1065586
dblp:conf/dac/Heidergott05
fatcat:2i7pofayvva33m6nleyaw64qfy
Volumetric signal processing hardware acceleration for mine detection
2003
Detection and Remediation Technologies for Mines and Minelike Targets VIII
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Digital signal processing algorithms for the detection of landmines using ground penetrating radar are computationally intensive if not due to algorithmic complexity, then due to the vast quantity of data ...
This is a viable alternative for the acceleration of digital signal processing and directly results in an increase in mine detection area coverage rates for a relatively small investment. ...
An error analysis of truncation of the results in this manner has not been done. ...
doi:10.1117/12.487730
fatcat:3xwo7mgy6vbizc4dxsa67jtkxu
A 500-mb/s soft-output viterbi decoder
2003
IEEE Journal of Solid-State Circuits
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Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-m CMOS technology. ...
These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit. ...
INTRODUCTION T URBO CODES consist of two or more convolutional codes concatenated through an interleaver in a parallel or serial structure. ...
doi:10.1109/jssc.2003.813250
fatcat:ftaulni5gbeiriikyhqvznhzsi
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study
2007
Journal of Signal Processing Systems
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they are used in critical missions. ...
The fault tolerance of these devices in radiation environments is traditionally analyzed and increased by means of soft error protection mechanisms as EDAC codes or physical interleaving. ...
References [16, 17] propose system knowledge based solutions for the fast Fourier transform (FFT), using different properties of the discrete Fourier transform (DFT) for the concurrent error detection ...
doi:10.1007/s11265-007-0154-6
fatcat:f46fav2xjbam7ihw7cucr63oj4
Table of contents
2017
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
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for HEVC Encoder
S-67 -A Convolutional Neural Network Approach for Half-Pel Interpolation in Video Coding
S-68 -Fast Rate Distortion Optimization with Adaptive Context Group Modeling for HEVC
S- ...
Video Encoding Scheme to Enhance Error Concealment of Intra Frames
Video Streaming Optimization Using Degradation Estimation with Unequal Error Protection
Multiply and Filter: An Universal Measurement ...
doi:10.1109/iscas.2017.8049750
fatcat:csazlovzq5g4bmzlf7uss65sy4
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