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Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration

Daniel Casini, Paolo Pazzaglia, Alessandro Biondi, Marco Di Natale
2022 Journal of systems architecture  
task, and (iv) selects which computations to accelerate, seeking for the most convenient trade-off between the smaller worst-case execution time provided by accelerators and synchronization and queuing  ...  To this end, this paper proposes a holistic framework to help designers partition real-time applications on heterogeneous platforms with hardware accelerators.  ...  For example, a computation may start on a processor core, continue on a hardware accelerator, and complete again on a core.  ... 
doi:10.1016/j.sysarc.2022.102416 fatcat:4ucvbckmjbbybc3lgz3xn6ymea

A Framework for the Development of Parallel and Distributed Real-Time Embedded Systems

Ricardo Garibay-Martinez, Luis Lino Ferreira, Luis Miguel Pinho
2012 2012 38th Euromicro Conference on Software Engineering and Advanced Applications  
The allocation of P/D tasks is later extended by considering distributed multi-core nodes. The extension is based on the constraint programming approach.  ...  Despite the fact that parallel computations in multi-processors can offer an increased processing capacity, the multi-threaded parallel real-time task models have not considered the cases in which a distributed  ...  An interesting survey on relevant techniques for multi-core (a.k.a. multi-processor) executing sequential real-time tasks is presented in (Davis and Burns, 2011) .  ... 
doi:10.1109/seaa.2012.60 dblp:conf/euromicro/Garibay-MartinezFP12 fatcat:ennxrr2m5vfbngbdedp56nje2e

Worst-case throughput analysis of real-time dynamic streaming applications

Firew Siyoum, Marc Geilen, Orlando Moreira, Henk Corporaal
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
Contemporary embedded wireless and multimedia applications are typically implemented on a Multiprocessor System-on-Chip (MPSoC) for power and performance reasons.  ...  These applications change their graph structure, data rates and computation loads, depending on their operating modes.  ...  Multi-core architectures for embedded streaming applications combine homogeneous and heterogeneous multiprocessing.  ... 
doi:10.1145/2380445.2380517 dblp:conf/codes/SiyoumGMC12 fatcat:2vxjwmsjfvaf3dnfsm4k4dmwra

Dependable embedded systems

2008 2008 6th IEEE International Conference on Industrial Informatics  
Titles in the Series cover a focused set of embedded topics relating to traditional computing devices as well as hightech appliances used in newer, personal devices, and related topics.  ...  The authors also would like to thank STMicroelectronics for the cooperation on FDSOI technology.  ...  It was a tremendous help to see to possibilities of FDSOI in silicon very early on.  ... 
doi:10.1109/indin.2008.4618103 fatcat:hal6brsgsjg5rlo3u5xil46pxi

Data-Age Analysis for Multi-Rate Task Chains under Timing Uncertainty

Pourya Gohari, Mitra Nasri, Jeroen Voeten
2022 Proceedings of the 30th International Conference on Real-Time Networks and Systems  
We develop a technique to compute lower and upper bounds on the data age of multi-rate task chains that execute upon a heterogeneous computing platform using a job-level fixed-priority scheduling policy  ...  Our evaluations on an industrial case study as well as synthetic task sets show that our analysis reduces the overestimation of the data age by 36% on average (and up to 42%) in comparison to the state  ...  A PE can refer to a processor core or an accelerator that is embedded on a chip (such as NVIDIA TX2 or NVIDIA AGX Xavier).  ... 
doi:10.1145/3534879.3534893 fatcat:domon7pfk5dytbflrajbv3accq

A Survey of Techniques for Reducing Interference in Real-time Applications on Multicore Platforms

Tamara Lugo, Santiago Lozano, Javier Fernandez, Jesus Carretero
2022 IEEE Access  
This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020.  ...  It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis.  ...  The proposal extends the optimal Hetero-Fair algorithm [202] to be applied on generic heterogeneous platforms consisting of more than two processor types. Bertout et al.  ... 
doi:10.1109/access.2022.3151891 fatcat:vutgetjua5byxczcivmw2esqtq

The Rubus component model for resource constrained real-time systems

Kaj Hanninen, Jukka Maki-Turja, Mikael Nolin, Mats Lindberg, John Lundback, Kurt-Lennart Lundback
2008 2008 International Symposium on Industrial Embedded Systems  
Based on these results, the thesis presents a novel component model for development of resource constrained real-time systems.  ...  In an evaluation, the thesis show that the analysis method is both fast and that it gives tight bounds on the resulting stack usage, which makes it suitable for industrial use.  ...  Processors for embedded systems have only a fraction of the processing power of desktop computers.  ... 
doi:10.1109/sies.2008.4577697 dblp:conf/sies/HanninenMNLLL08 fatcat:47phf5ls3fcjfn446dcshfevoy

OASIcs, Volume 77, NG-RES'20, Complete Volume [article]

Marko Bertogna, Federico Terraneo
2020
Energy optimization for real-time multiprocessor system-on-chip with optimal DVFS and DPM combination. ACM Trans. Embedded Comput. Syst., 13  ...  2:12 Energy Minimization in DAG Scheduling on MPSoCs at Run-Time Evripidis Bampis, Dimitrios Letsios, and Giorgio Lucarelli. A note on multiprocessor speed scaling with precedence constraints.  ...  Second, the WCRT of each migrating task and the WCTT of its i/o messages may change after the migration; The WCRT of a task may change, e.g, if its pre-and post-migration cores are heterogeneous.  ... 
doi:10.4230/oasics.ng-res.2020 fatcat:2bxbtactwvhv7d76odjlk2xdmu

OASIcs, Volume 55, WCET'16, Complete Volume [article]

Martin Schoeberl
2016
The author would like to thank the organizers, the speakers and the participants of the Optimizing Real-Time Systems workshop on Parallelization of real-time tasks 1 : they have inspired this paper.  ...  We want to thank Bendikt Huber for porting the Lift benchmark from Java to C. We want to thank Niklas Holsti from Tidorum Ltd for contributing DEBIE in open-source.  ...  for Timing Analysis on Embedded Multi-Cores for Timing Analysis on Embedded Multi-Cores Figure 1 A 1 Figure1A parallel task defined as a set of sub-tasks subject to precedence constraints (DAG).  ... 
doi:10.4230/oasics.wcet.2016 fatcat:2smyzkdh7rdndcptwasq4qsfue

Efficient Adaptive Hard Real-time Multi-processor Systems

Stefanos Skalistis
2017
Homogeneous Architecture Types The focus of this dissertation is on homogeneous multi-processor architectures, with the PEs being general purpose cores, for reasons explained in the Introduction.  ...  Thank you Abbas, Alex, Androklis, Apostolos, Ashkan, i 1 Introduction The need of Multi-processors Modern computing systems are based on multi-processor systems, i.e. processors with more than one processing  ...  Adaptive & Efficient Hard Real-time Systems Carry out research on the deployment and execution of highly-parallelisable applications with real-time constraints on many-core architectures with network-on-chip  ... 
doi:10.5075/epfl-thesis-8146 fatcat:fzudr3eycjhfjivvcqzw2gt2ri

Tight integration of cache, path and task-interference modeling for the analysis of hard real time systems

Jan C. Kleinsorge, Technische Universität Dortmund, Technische Universität Dortmund
2015
Today this model is outdated as it relies on technical assumptions that are not feasible on modern processor architectures any longer.  ...  In addition, we propose two new estimation methods for CRPD based on the explicit elimination of infeasible task interference scenarios.  ...  The final graph will be a DAG for which weight is computed once again.  ... 
doi:10.17877/de290r-16409 fatcat:j4ln2x56trbyjgpyw2bopqfo6q