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Page 5966 of Mathematical Reviews Vol. , Issue 94j [page]

1994 Mathematical Reviews  
(English summary) Computer aided verification (Elounda, 1993), 463-478, Lecture Notes in Comput. Sci., 697, Springer, Berlin, 1993.  ...  (English summary) Computer aided verification (Montreal, PQ, 1992), 302-315, Lecture Notes in Comput. Sci., 663, Springer, Berlin, 1993.  ... 

Page 2217 of Mathematical Reviews Vol. , Issue 92d [page]

1992 Mathematical Reviews  
Computer-aided verification 90 (New Brunswick, NJ, 1990), 321-340, DIMACS Ser. Discrete Math. Theoret. Comput. Sci., 3, Amer. Math. Soc., Providence, RI, 1991.  ...  Computer-aided verification ’90 (New Brunswick, NJ, 1990), 231-250, DIMACS Ser. Discrete Math. Theoret. Comput. Sci., 3, Amer. Math. Soc., Providence, RI, 1991.  ... 

Page 5384 of Mathematical Reviews Vol. , Issue 94i [page]

1994 Mathematical Reviews  
computer-aided ver- ification (214-223); Jerry R.  ...  {The papers of mathematical interest that appear to be in final form are being reviewed individually.} 94i:68187 68Q60 68-06 % Computer aided verification.  ... 

A Path Construction Algorithm for Translation Validation Using PRES+ Models

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal, Kunal Banerjee, Krishnam Raju Duddu
2016 Parallel Processing Letters  
Verification of Code Motion Techniques using Value Propagation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 8, 2014, pages: 1180-1193. 4.  ...  Parallel Processing Letters (PPL), (accepted). 2. Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal. Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs.  ... 
doi:10.1142/s0129626416500109 fatcat:wvfslscsbvab5c6h7ase5423ny

From UML activity diagrams to specification requirements

Doron Drusinsky
2008 2008 IEEE International Conference on System of Systems Engineering  
Formal verification of system-of-systems uses computer-based techniques to assure that the behavior of a subject system of systems complies with its formal correctness specifications.  ...  This paper describes the process of identifying NL requirements of interest from UML analysis diagrams such as activity diagrams) and Message Sequence Diagrams.  ...  The extension of this process, discussed in [Dr1] , enables computer aided validation and verification of the systems behavior with respect to these concerns.  ... 
doi:10.1109/sysose.2008.4724143 dblp:conf/sysose/Drusinsky08 fatcat:ksg4a3ikircrhicd6art7ki2wq

Page 8509 of Mathematical Reviews Vol. , Issue 2002K [page]

2002 Mathematical Reviews  
., in Computer aided verification (New Brunswick, NJ, 1996), 269-276; Lecture Notes in Comput. Sci., 1102, Springer, New York, 1996; C. Baier, J.-P. Katoen and H.  ...  Baier et al., in Computer aided verification (Chicago, IL, 2000), 358-372, Lecture Notes in Comput. Sci., 1855, Springer, Berlin, 2000; Zbl 0974.68017] can be employed.”  ... 

Model Checking Data-Dependent Real-Time Properties of the European Train Control System

Johannes Faber, Roland Meyer
2006 2006 Formal Methods in Computer Aided Design  
the Formal Methods in Computer Aided Design (FMCAD'06) 0-7695-2707-8/06 $20.00 © 2006  ...  − StopDist Proceedings of the Formal Methods in Computer Aided Design (FMCAD'06) 0-7695-2707-8/06 $20.00 © 2006 TABLE I I EXPERIMENTAL RESULTS (ATHLON XP 2200+, 512 MB RAM) Task Locs Trans Vars Preds  ... 
doi:10.1109/fmcad.2006.21 dblp:conf/fmcad/FaberM06 fatcat:vfs5goch6rgcvmicw767dfdple

Page 2786 of Linguistics and Language Behavior Abstracts: LLBA Vol. 29, Issue 5 [page]

1995 Linguistics and Language Behavior Abstracts: LLBA  
-/speaker- independent model; speaker/text verification tests; 9512356 speech perception performance changes, Nucleus 22 channel cochlear implant/Tactaid tactile aid/conventional hearing aid use compari  ...  processing hypotheses; 9512462 Arabic/ French 2p et tng comparison, fundamental frequen- cy/hearing aid distortions difference; empirical data; educated French-proficient North African Arabic speakers  ... 

Formal Analysis and Verification of an OFDM Modem Design using HOL

Abu M. Abdullah, Behzad Akbarpour, Sofiene Tahar
2006 2006 Formal Methods in Computer Aided Design  
In this paper we formally specify and verify an implementation of the IEEE802.11a standard physical layer based OFDM (Orthogonal Frequency Division Multiplexing) modem using the HOL (Higher Order Logic  ...  The versatile expressive power of HOL helped model the original design at all abstraction levels starting from a floating-point model to the fixed-point design and then synthesized and implemented in FPGA  ...  The goal is to achieve more efficient verification process. Proceedings of the Formal Methods in Computer Aided Design (FMCAD'06) 0-7695-2707-8/06 $20.00 © 2006  ... 
doi:10.1109/fmcad.2006.14 dblp:conf/fmcad/AbdullahAT06 fatcat:dkbv4hkwbzgmzgxwpz7ths7wue

Tampere Verification Tool [chapter]

Heikki Virtanen, Henri Hansen, Antti Valmari, Juha Nieminen, Timo Erkkilä
2004 Lecture Notes in Computer Science  
Tampere Verification Tool (TVT) is a collection of programs for automated verification of concurrent and reactive systems.  ...  Furthermore, it contains three types of state proposition-like notions to support on-the-fly verification, and one state proposition to exploit partially defined processes.  ...  The development of TVT was supported by Nokia Research Center, The Technology Development Centre of Finland and Emil Aaltonen Foundation.  ... 
doi:10.1007/978-3-540-24730-2_12 fatcat:q2dpnamc6zg3nkjjroy3e5vi3i

A Framework for Automated Performance Tuning and Code Verification on GPU Computing Platforms

Allison S. Gehrke, Ilkyeun Ra, Daniel A. Connors
2011 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum  
For the most part, current scientists only leverage multi-core and GPU (Graphical Processing Unit) computing platforms after painstakingly uncovering the inherent task and data-level parallelism in their  ...  In many cases, the development does not realize the full potential of the parallel hardware.  ...  ACKNOWLEDGMENT Allison Gehrke is an Achievement Rewards for College Scientists (ARCS) scholar and gratefully acknowledges the support of the ARCS foundation.  ... 
doi:10.1109/ipdps.2011.390 dblp:conf/ipps/GehrkeRC11 fatcat:wsgr45tm3ffvbg3dvrj2l2766a

Teaching Formal Models of Concurrency Specification and Analysis

N. V. Shilov
2016 Modelirovanie i Analiz Informacionnyh Sistem  
Due to this reason, there is a need of research, study and teaching of formal models of concurrency and methods of distributed system verification.  ...  This interest is based on availability of supercomputers, computer clusters and powerful graphic processors for computational mathematics and simulation.  ...  And the puzzle about four men and a boat helps to teach and learn some formal models and theories of concurrency.  ... 
doi:10.18255/1818-1015-2015-6-783-794 fatcat:rezo4znzxbat5emrxs25lyws3u

Automatic synthesis of computation interference constraints for relative timing verification

Yang Xu, Kenneth S. Stevens
2009 2009 IEEE International Conference on Computer Design  
The process of creating path-based RT constraints has previously been done by hand with the aid of a formal verification engine.  ...  This paper describes an algorithm for automatic generation of RT constraints based on signal traces generated from a formal verification (FV) engine that supports relative timing constraints.  ...  The process of creating path-based RT constraints has previously been done by hand with the aid of a formal verification engine.  ... 
doi:10.1109/iccd.2009.5413183 dblp:conf/iccd/XuS09 fatcat:gng5cbexyjavhpfowpueonjhhe

Artificial Intelligence Research at General Electric

Larry Sweet
1985 The AI Magazine  
Further, new application domains such as computer-aided design (CAD), computer-aided manufacturing (CAM), and image understanding based on formal logic require novel concepts in knowledge representation  ...  and applications pursued in parallel efforts by operating departments The fundamental research and advanced applications activities are strongly coupled, providing research teams with opportunities for  ...  Parallel Processing Computer Architectures The Connection Machine, originally conceived at MIT, is a massively parallel Single Instruction, Multiple Datastream (SIMD) machine for real-time AI applications  ... 
dblp:journals/aim/Sweet85 fatcat:4dukvfgf6vde5e5n5skwm6bw54

A Hardware Architecture for Switch-Level Simulation

W.J. Dally, R.E. Bryant
1985 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
INTRODUCTION A s THE complexity of VLSI circuits approaches 10 6 devices, the computational requirements of design verification are exceeding the capacity of general purpose computers.  ...  The bur den of simulation is compounded by the iterative nature of the design process.  ... 
doi:10.1109/tcad.1985.1270120 fatcat:pclvgk6zqzcrtkfsdf42pn5d44
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