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Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits

G. De Micheli, A.R. Newton, A. Sangiovanni-Vincentelli
1983 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
De Micheli, "An Outlook on Design Technologies for Future Integrated Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 6, pp. 777-790, 2009. 145.  ...  De Micheli, "Performance-Oriented Synthesis of Large Scale Domino CMOS Circuits," IEEE Transac- tions on CAD/ICAS, Vol.  ... 
doi:10.1109/tcad.1983.1270034 fatcat:etfup6qaszbxvd7bialawzqk2u

Design methodologies, models and tools for very-large-scale integration of NEM relay-based circuits

Tian Qin, Sunil Rana, Dinesh Pamunuwa
2015 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
Design methodologies, models and tools for very-large-scale integration of NEM relay-based circuits. In  ...  With such capability, the proposed design framework can potentially be used for increasing design productivity for any heterogeneously integrated CMOS-NEM design (e.g.  ...  It is however too time consuming to run an analog simulation for full chip-level verification of large designs.  ... 
doi:10.1109/iccad.2015.7372630 dblp:conf/iccad/QinRP15 fatcat:ciaktdjalrbhfhc3gxjpq4e6yy

Benchmarking for Large-Scale Placement and Beyond

S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh, P.H. Madden
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.  ...  In this paper we review motivations for benchmarking, especially for commercial EDA, analyze available benchmarks, and point out major pitfalls in benchmarking.  ...  Andrew Kahng (UCSD) and Xiaojian Yang (Synplicity) for technical discussions and help with placement tools.  ... 
doi:10.1109/tcad.2004.825852 fatcat:gu2ogxlkjjdvnd6rv7rf2ftmiq

MB$^{\ast}$-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design

Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Further, unlike previous works, the MB * -tree scales very well as the circuit size increases.  ...  In this paper, we present an agglomeratively multilevel floorplanning/placement framework based on the B * -tree representation called MB * -tree to handle the floorplanning and packing for large-scale  ...  Lee ing and optimizing large-scale modules are essential for such large designs.  ... 
doi:10.1109/tcad.2007.891368 fatcat:65ejkufafrgm3ia473ledjz6p4

Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations

Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The large-scale process and environmental variations for today's nanoscale ICs require statistical approaches for timing analysis and optimization.  ...  An efficient algorithm with incremental analysis capability is developed for fast sensitivity computation that has linear runtime complexity in circuit size.  ...  Addressing the nanoscale manufacturing and design realities requires a paradigm shift in the current design methodology such that large-scale variations are considered at all levels of design hierarchy  ... 
doi:10.1109/tcad.2008.923241 fatcat:v45vt26mznfptac3j3rh2mqkzy

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning

Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We present in this paper a new interconnect-driven multilevel floorplanner, called interconnect-driven multilevelfloorplanning framework (IMF), to handle large-scale buildingmodule designs.  ...  In particular, IMF scales very well as the circuit size increases.  ...  The CPU times for B * -tree and Parquet grow dramatically as the circuit size increases while both the IMF+AFF and Capo can scale to very large-scale designs.  ... 
doi:10.1109/tcad.2007.907065 fatcat:z355zkpwxnggpofhrwwqhnfaym

A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation

Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng
2012 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we develop a practical two-stage strategy to remove the singularity in MNA equations of large-scale circuit networks.  ...  Fast full-chip time-domain simulation calls for advanced numerical integration techniques with capability to handle the systems with (tens of) millions of variables resulting from the modified nodal analysis  ...  Acknowledgment The reviewers' comments that led to significant improvement for the paper are highly appreciated.  ... 
doi:10.1109/tcad.2012.2184761 fatcat:nsxj4zgmabd2dfvqcfhdytx5hy

Time-Domain Orthogonal Finite-Element Reduction-Recovery Method for Electromagnetics-Based Analysis of Large-Scale Integrated Circuit and Package Problems

Duo Chen, Dan Jiao
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
A time-domain orthogonal finite-element reductionrecovery method is developed to overcome the large problem sizes encountered in the simulation of large-scale integrated-circuit and package problems.  ...  Based on this set of bases, an arbitrary 3-D multilayered system such as a combined package and die is reduced to a single-layer system with negligible computational cost.  ...  Chakravarty of Intel Corporation for providing the measured data and Dr. W. Shi of Intel Corporation for providing the package structures.  ... 
doi:10.1109/tcad.2009.2021010 fatcat:43ga2zck4jclrij76rcljl53je

A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits

Jongwon Lee, Duo Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Dan Jiao
2012 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
It successfully solves a quadratic eigenvalue problem of over 2.5 million unknowns associated with a large-scale 3-D on-chip circuit embedded in inhomogeneous materials in 40 min on a single 3 GHz 8222SE  ...  Index Terms-Arnoldi iteration, fast solvers, finite element methods, full-wave analysis, integrated circuits, quadratic eigenvalue problem, resonance analysis.  ...  His current research interests include physical design of very large-scale integrated circuits and modeling and analysis of large-scale systems. Dr.  ... 
doi:10.1109/tcad.2011.2170989 fatcat:zewkyjgvy5cmpanybaqnpbryfi

A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks

Stephen Cauley, Venkataramanan Balakrishnan, Cheng-Kok Koh
2010 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Through the use of additional computational resources, this distributed computing technique facilitates the simulation of large-scale power/ground networks.  ...  The parallel matrix inversion algorithm shows substantial computational improvement over the best known direct and iterative numerical techniques that are applicable to these large-scale simulation problems  ...  Increases to integration density have necessitated the use of large-scale power mesh structures, and with the scaling of voltages the need for accurate simulation of these structures is crucial.  ... 
doi:10.1109/tcad.2010.2042901 fatcat:xerdtmqo5bc7fkjdvtdelhym5u

A new multilevel Green's function interpolation method for large-scale low-frequency EM simulations

Hao Gang Wang, Chi Hou Chan, Leung Tsang
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, a new multilevel Green's function interpolation method (MLGFIM) is presented to solve integral equations for large-scale electrostatic problems.  ...  The MLGFIM is used to extract the capacitances encountered in radio frequency integrated circuits (RFICs) and microelectromechanical systems.  ...  ACKNOWLEDGMENT The authors thank anonymous reviewers for giving many constructive comments.  ... 
doi:10.1109/tcad.2005.850804 fatcat:tj7zxjz27fatxcnaba3j36okpq

RWCap: A Floating Random Walk Solver for 3-D Capacitance Extraction of Very-Large-Scale Integration Interconnects

Wenjian Yu, Hao Zhuang, Chao Zhang, Gang Hu, Zhi Liu
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
A floating random walk (FRW) solver, called RWCap, is presented for the capacitance extraction of verylarge-scale integration (VLSI) interconnects.  ...  The experiments on an 8-core CPU machine show that the parallel RWCap is over 6× faster than its serial-computing version.  ...  The 3-D FRW algorithm for capacitance extraction has been developed and applied to the design and analysis of very-large-scale integration (VLSI) circuits [10] - [12] .  ... 
doi:10.1109/tcad.2012.2224346 fatcat:55uc4wznevb6doarov4o4hnk5y

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Legalization (LG), physical design, placement.  ...  Hence, modern placers need to handle the instances with large-scale mixed-size macros and standard cells.  ...  After computing the CG direction d k , the step size α k is computed by α k = sw b d k 2 (12) where s is a user-specified scaling factor, and w b is the bin width.  ... 
doi:10.1109/tcad.2008.923063 fatcat:sa7i3ifyuzdejpgy4qtvw7agky

Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks

Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Chung-Kuan Cheng
2016 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We design an algorithmic framework using matrix exponentials for time-domain simulation of power delivery network (PDN).  ...  Our framework can reuse factorized matrices to simulate the large-scale linear PDN system with variable stepsizes.  ...  Due to the enormous size of modern designs and long simulation runtime of many cycles, instead of general nonlinear circuit simulation [16] , [17] , PDN is often modeled as a large-scale linear circuit  ... 
doi:10.1109/tcad.2016.2523908 fatcat:2jok6mmpi5amjdkxzfl3dvptgi

Background memory area estimation for multidimensional signal processing systems

F. Balasa, F. Catthoor, Hugo De Man
1995 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
RESEARCH INTERESTS: Electronic Design Automation (EDA, CAD VLSI) • Algorithms for physical design automation • Memory management algorithms for digital signal processing, multimedia applications, embedded  ...  -Aided Design of Integrated Circuits and Systems, Vol. 16, No. 2, pp. 133-145, Feb. 1997. J5. F. Balasa, K.  ...  -Aided Design of Integrated Circuits and Systems, Vol. 19, No. 7, pp. 721-731, July 2000. J6. F. Balasa, S.C.  ... 
doi:10.1109/92.386218 fatcat:kckotwklmren7nofrertj635xi
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