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How to Break Secure Boot on FPGA SoCs Through Malicious Hardware [chapter]

Nisha Jacob, Johann Heyszl, Andreas Zankl, Carsten Rolfes, Georg Sigl
2017 Lecture Notes in Computer Science  
hardware designs, are used.  ...  In this contribution, we demonstrate how an FPGA hardware design can compromise the important secure boot process of the main software system to boot from a malicious network source instead of an authentic  ...  malicious hardware in the FPGA of FPGA SoCs.  ... 
doi:10.1007/978-3-319-66787-4_21 fatcat:n2fz4op665caba27jyp55u6pma

Pro-Active Policing and Policy Enforcement Architecture for Securing MPSoCs

Fahad Siddiqui, Matthew Hagan, Sakir Sezer
2018 2018 31st IEEE International System-on-Chip Conference (SOCC)  
The use of vulnerable third-party IP can open the door to attacks such as Hardware Trojans and malware, that can be launched within any device using the compromised IP [11] , [12] , [13] .  ...  In case of unexpected behaviour, for example a malicious action initiated by a Hardware Trojan or launching of a compromised application by an adversary, the system can take both pro-active countermeasures  ... 
doi:10.1109/socc.2018.8618531 dblp:conf/socc/SiddiquiHS18 fatcat:4rxzt7pdwra6xgx7mrzytdpqou

Ransomware Attack as Hardware Trojan: a Feasibility and Demonstration Study

Felipe Almeida, Malik Imran, Jaan Raik, Samuel Pagliarini
2022 IEEE Access  
In order to discuss the detectability of the malicious logic, the hardware ransomware is inserted in a complex system on chip (SoC).  ...  INDEX TERMS Ransomware attack, hardware security, hardware trojan horse, malicious logic, ASIC.  ...  Representative ASIC design flow, possible attackers, and compromised design artifacts. FIGURE 2 . 2 FIGURE 2. Block diagram of the proposed hardware ransomware. FIGURE 3 . 3 FIGURE 3.  ... 
doi:10.1109/access.2022.3168991 fatcat:movumqapszaexciqyc4wfxogkq

BYOTee: Towards Building Your Own Trusted Execution Environments Using FPGA [article]

Md Armanuzzaman, Ziming Zhao
2022 arXiv   pre-print
We implement a BYOTee system for the Xilinx System-on-Chip (SoC) FPGA.  ...  BYOTee creates enclaves with customized hardware TCBs, which include softcore CPUs, block RAMs, and peripheral connections, in FPGA on demand.  ...  The nature of FPGA enables on-demand configurations and reconfigurations of enclaves' hardware TCBs, which may include softcore CPUs, Block RAM based (BRAM; same as Static RAM on known SoC FPGA devices  ... 
arXiv:2203.04214v2 fatcat:qhlcarxo2fa3raevvilhrhkz7q

Ten years of hardware Trojans: a survey from the attacker's perspective

Mingfu Xue, Chongyan Gu, Weiqiang Liu, Shichao Yu, Máire O'Neill
2020 IET Computers & Digital Techniques  
intellectual property (3PIP) vendor attacks, computer-aided design (CAD) tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field programmable gate array (FPGA  ...  In the last decade, hardware Trojan has emerged as a serious concern in integrated circuit (IC) industry. As such, hardware Trojan detection techniques have been studied extensively.  ...  Some fragile hardware watermarking structures can also be used. Once the integrity of the hardware is compromised, the watermark will be broken.  ... 
doi:10.1049/iet-cdt.2020.0041 fatcat:7ugjmpblfjdippalfhovzmgaky

A novel PUF-based encryption protocol for embedded System on Chip

Alexandra Stanciu, Florin Dumitru Moldoveanu, Marcian Cirstea
2016 2016 International Conference on Development and Application Systems (DAS)  
The proposed new method is based on encrypted and authenticated communications between the microprocessor cores, FPGA fabric and peripherals inside the SoC.  ...  This paper presents a novel security mechanism for sensitive data stored, acquired or processed by a complex electronic circuit implemented as System-on-Chip (SoC) on an FPGA reconfigurable device.  ...  Dividing SoC peripherals into domains The Spartan 3E is a small FPGA family with limited hardware resources. However, the FPGA may be divided in small areas, one for each SoC domain.  ... 
doi:10.1109/daas.2016.7492566 fatcat:3irwp74mafhtpazaqbhvzepeu4

CARE: Lightweight Attack Resilient Secure Boot Architecturewith Onboard Recovery for RISC-V based SOC [article]

Avani Dave, Nilanjan Banerjee, Chintan Patel
2021 arXiv   pre-print
Consequently, an attacker can exploit security vulnerabilities and compromise these devices.  ...  In this context, the secure boot becomes a useful security mechanism to verify the integrity and authenticity of the software state of the devices.  ...  The test setup first uses both hardware and software [19] implementation of cryptographic-core running on FPGA for performance evaluation, as shown in Table 1.  ... 
arXiv:2101.06300v1 fatcat:b7as4syt3zdp3nrxawftg5l35m

A PUF-based cryptographic security solution for IoT systems on chip

Alexandra Balan, Titus Balan, Marcian Cirstea, Florin Sandu
2020 EURASIP Journal on Wireless Communications and Networking  
The integration of multicore processors and peripherals from multiple intellectual property core providers as hardware components of IoT multiprocessor systems-on-chip (SoC) represents a source of security  ...  The mechanism employed in this approach uses physically unclonable functions (PUF) and symmetric cryptography in order to encrypt the transferred messages within the SoC between the microprocessor and  ...  All of these FPGAs have the necessary hardware resources in order to implement a SoC with the presented security mechanism.  ... 
doi:10.1186/s13638-020-01839-6 fatcat:okq5soehg5atfj52zozazvt22i

Towards the Security of Motion Detection-based Video Surveillance on IoT Devices

Xianglong Feng, Mengmei Ye, Viswanathan Swaminathan, Sheng Wei
2017 Proceedings of the on Thematic Workshops of ACM Multimedia 2017 - Thematic Workshops '17  
We implement the security framework on an ARM system on chip (SoC).  ...  surveillance enabled by Internet of ings (IoT) devices, such as smart cameras, has become a popular set of applications recently with the trend of adopting IoT in multimedia signal processing and smart home use  ...  Figure 6 : 6 Hardware isolation framework. Figure 7 : 7 ARM TrustZone con guration to block malicious accesses to the PL.  ... 
doi:10.1145/3126686.3126713 dblp:conf/mm/FengYS017 fatcat:yj2dzbg6qfcdfn3kwsvmcw4lg4

Towards a Trusted Execution Environment via Reconfigurable FPGA [article]

Sérgio Pereira, David Cerdeira, Cristiano Rodrigues, Sandro Pinto
2021 arXiv   pre-print
Trusted Execution Environments (TEEs) are used to protect sensitive data and run secure execution for security-critical applications, by providing an environment isolated from the rest of the system.  ...  However, over the last few years, TEEs have been proven weak, as either TEEs built upon security-oriented hardware extensions (e.g., Arm TrustZone) or resorting to dedicated secure elements were exploited  ...  FPGA-based TEEs Recently, FPGAs start being used to create isolated environments for performing both software and hardware security sensitive operations.  ... 
arXiv:2107.03781v1 fatcat:cy35x5ixhzd5joqc2hco6ydtiu

Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically

Matthew Hicks, Murph Finnicum, Samuel T. King, Milo M. K. Martin, Jonathan M. Smith
2010 2010 IEEE Symposium on Security and Privacy  
This paper presents a hybrid hardware/software approach to defending against malicious hardware.  ...  During the design verification phase, BlueChip invokes a new technique, unused circuit identification (UCI), to identify suspicious circuitry-those circuits not used or otherwise activated by any of the  ...  The malicious logic records the address of the block and the redirection address in hardware registers.  ... 
doi:10.1109/sp.2010.18 dblp:conf/sp/HicksFKMS10 fatcat:ugy6qqmkmrhlrmwmwgn3rsv6rm

Towards a Safe and Secure Internet of Things Critical Infrastructure

Maha Alqallaf
2021 Zenodo  
Specifically, we have proposed (1) hardware based schemes for establishment of root of trust; (2) the design of a reliable and secure key generator and management system using SoC FPGA; (3) development  ...  Index Terms—Internet of Things, hardware-based security, embedded systems, SoC, FPGA, secure communications  ...  Using dedicated hardware assist (e.g., SoC, FPGA) can relieve the burden on processors.  ... 
doi:10.5281/zenodo.4577525 fatcat:gjhzrn7tszgs5fxdjuwjkzngeq

SideLine: How Delay-Lines (May) Leak Secrets from your SoC [article]

Joseph Gravellier, Jean-Max Dutertre, Yannick Teglia, Philippe Loubet Moundi
2020 arXiv   pre-print
To meet the ever-growing need for performance in silicon devices, SoC providers have been increasingly relying on software-hardware cooperation.  ...  After providing a detailed method on how to access and convert delay-line data into power consumption information, we demonstrate that these entities can be used to perform remote power side-channel attacks  ...  This section discloses a second attack path that allows the hijacking of a programmable delay-block and its malicious use to perform core-vs-core power SCAs.  ... 
arXiv:2009.07773v1 fatcat:2omaysxdondn5hgclfo65ak5wa

Secure Boot for Reconfigurable Architectures

Ali Shuja Siddiqui, Yutian Gui, Fareena Saqib
2020 Cryptography  
This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration.  ...  This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates.  ...  How to break secure boot on FPGA SoCs through malicious hardware.  ... 
doi:10.3390/cryptography4040026 fatcat:rrutti77gnaspirfcmz4p22bbq

Embedded Policing and Policy Enforcement based Security in the era of Digital-Physical Convergence for Next-Generation Vehicular Electronics [article]

Fahad Siddiqui, Matthew Hagan, Sakir Sezer
2020 arXiv   pre-print
One approach to this research problem is to introduce fail-over mechanisms that can detect unexpected or malicious behaviours, caused by attack or malfunction, and pro-actively respond to control and minimise  ...  lists: Hardware components hold a list of approved CAN messages IDs to block malicious CAN messages originating either from a compromised or an introduced malicious node. • Error Limit Check: Hardware-based  ...  Decision block The decision block detects compromised service, malfunction or malicious activity, such as modification of security attributes, as shown in Figure 5 and 6.  ... 
arXiv:2004.10672v1 fatcat:hda7w26qnzdspp5bmlyd6ku5ze
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