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Design and Implementation of Deep Depth Decision Algorithm for Complexity Reduction in High Efficiency Video Coding (HEVC)

Helen K Joy, Manjunath R Kounte, B K Sujatha
2022 International Journal of Advanced Computer Science and Applications  
In the first step, the modelling of the deep depth decision algorithm is done with optimum specifications using convolutional neural network (CNN).  ...  to predict and perform this process.  ...  Fig. 1(b) shows the level and depth of CTU. Understanding this depth concept [6] helps in designing deep CNN [13] algorithm to predict depth and thus to make intra prediction less complex.  ... 
doi:10.14569/ijacsa.2022.0130168 fatcat:g3nqyowfi5dbne77zw5ffgjcye

MOD-CHAR: an implementation of Char's spanning tree enumeration algorithm and its complexity analysis

R. Jayakumar, K. Thulasiraman, M.N.S. Swamy
1989 IEEE Transactions on Circuits and Systems  
Abstruct -An implementation, called MOD-CHAR, of Char's spanning tree enumeration algorithm [3] is discussed. Two complexity analyses of MOD-CHAR are presented.  ...  The class of graphs for which MOD-CHAR and, hence, Char's algorithm has linear time complexity per spanning tree generated is identified.  ...  Our objective here is to explore further the structure of Char's algorithm and to exploit this structure to design an implementation of the algorithm which leads to more refined complexity results.  ... 
doi:10.1109/31.20199 fatcat:6p4rf3zj5nebrii7zse247fr2e

Computer aided implementation of complex algorithms on DSP's using automatic scaling

K. Kassapoglou, M. Vetterli
ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing  
Each case is illustrated by an example (FFT and Recursive Least-Squares algorithms).  ...  A methodology for transforming complex floating-point algorithms into correct fixed-point DSP programs is presented.  ...  Introduction Most current digital signal processors (DSP's) use fixed-point arithmetic, thus leading t o scaling and precision problems when implementing complex algorithms.  ... 
doi:10.1109/icassp.1987.1169879 dblp:conf/icassp/KassapoglouV87 fatcat:cbiit3eipzgg3nngj7ijgylcse

A Novel Recursive Algorithm for Efficient ZF-OSIC Detection in a V-BLAST System

Zuo-Liang Yin
2011 KSII Transactions on Internet and Information Systems  
A fast implementation of the proposed algorithm is developed and its complexity is analyzed in detail.  ...  To reduce the implementation complexity of the Vertical Bell Labs layered space-time (V-BLAST) systems with respect to the zero-forcing (ZF) criterion, a computationally efficient recursive algorithm is  ...  Solution: The estimate of the transmitted signal Fast Implementation and Evaluation of Implementation Complexity In this section, we evaluate the implementation complexity of the proposed algorithm and  ... 
doi:10.3837/tiis.2011.12.004 fatcat:veaasog7vfhhzn7xejbluhcetq

VLSI implementation of a hardware-optimized lattice reduction algorithm for WiMAX/LTE MIMO detection

Ameer Youssef, Mahdi Shabany, P. Glenn Gulak
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm.  ...  This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity.  ...  The VLSI implementation of our algorithm represents the first ASIC implementation of any LR algorithm that achieves ML diversity (such as LLL and SA type algorithms).  ... 
doi:10.1109/iscas.2010.5537810 dblp:conf/iscas/YoussefSG10 fatcat:d2tmyaa3mbacpbzyvz2cl5zqkq

Span Programs and Quantum Time Complexity

Arjan Cornelissen, Stacey Jeffery, Maris Ozols, Alvaro Piedrafita, Daniel Kráľ, Javier Esparza
2020 International Symposium on Mathematical Foundations of Computer Science  
time, query and space complexities and are a complete model of quantum algorithms.  ...  Span programs are an important model of quantum computation due to their correspondence with quantum query and space complexity.  ...  The variable time search result composes a set of arbitrary functions with the OR function and obtains a Grover-like speed-up in the query and time complexity of the resulting algorithm.  ... 
doi:10.4230/lipics.mfcs.2020.26 dblp:conf/mfcs/CornelissenJOP20 fatcat:sru2jqt3jzfl7km2z6ejzh4wta

Reduced-Complexity k-best Decoder for LTE Standard

Shirly Edward A., Malarvizhi S.
2015 International Journal of Multimedia and Ubiquitous Engineering  
This paper presents a VLSI implementation of reduced -complexity and reconfigurable MIMO(Multiple-Input Multiple-Output) signal detector targeting 3GPP-LTE standard.  ...  FPGA implementation of ML detector becomes infeasible as its complexity grows exponentially with the increase in number of antennas.  ...  In literature, some researchers divide the tree search into several parts [10, 11] and implement the K-best algorithm but still the complexity of the search does not decrease further.  ... 
doi:10.14257/ijmue.2015.10.3.36 fatcat:n4fonpqutbesrkdglobnphh5he

Another Motivation for Reducing the Randomness Complexity of Algorithms [chapter]

Oded Goldreich
2011 Lecture Notes in Computer Science  
We observe that the randomness-complexity of an algorithm effects the time-complexity of implementing a version of it that utilizes a weak source of randomness (through a randomness-extractor).  ...  This provides an additional motivation for the study of the randomness complexity of randomized algorithms.  ...  We also wish to thank Adi Akavia and Shafi Goldwasser for a discussion that led to the current essay.  ... 
doi:10.1007/978-3-642-22670-0_36 fatcat:xfjj2chdqfcxlfw2o2u476tmsi

VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection

L. Bruderer, C. Studer, M. Wenk, D. Seethaler, A. Burg
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
Comparisons with existing FPGA implementations show that our design outperforms state-of-the-art LR implementations in terms of hardware-efficiency and throughput.  ...  For this purpose, we introduce various algorithmic modifications that enable an efficient hardware implementation.  ...  Application of a complex-valued Givens rotation null the matrix elementR k,k−1 and update the corresponding elements ofR andQ, such that GT =QR.  ... 
doi:10.1109/iscas.2010.5537742 dblp:conf/iscas/BrudererSWSB10 fatcat:oa6yznsffrdg7dz67za5qiqfpq

Hybrid Lattice Reduction Algorithm And Its Implementation On An Sdr Baseband Processor For Lte

Ubaid Ahmad, Amir Amin, Rudy Lauwereins, Min Li, Sofie Pollin, Liesbet Van der Perre
2011 Zenodo  
Publication in the conference proceedings of EUSIPCO, Barcelona, Spain, 2011  ...  Implementations of these algorithms reported for ASIC [5] and FPGA [6] [7] [8] are essentially sequential and non-deterministic.  ...  Majority of the exiting work on lattice reduction algorithms aim at improving performance while sacrificing computational complexity and vice versa.  ... 
doi:10.5281/zenodo.42575 fatcat:5yucx5xj6fbrzadc7hj5xuhydy

Using local-spin k -exclusion algorithms to improve wait-free object implementations

James H. Anderson, Mark Moir
1997 Distributed computing  
Our k-exclusion algorithms are starvation-free, and are designed to be fast in the absence of contention, and to exhibit scalable performance as contention rises.  ...  The resulting \hybrid" object implementations combine the advantages of local-spin spin locks, which perform well in the absence of process delays (caused, for example, by preemptions), and wait-free algorithms  ...  Acknowledgement: We are grateful to the anonymous referees for their helpful comments, and to Phil McKinley and Chuck Severance of Michigan State University for their assistance with the use of their BBN  ... 
doi:10.1007/s004460050039 fatcat:vimlchgpjregvm3tn2h3i7cnju

On-Chip Implementation of High Speed and High Resolution Radix 2 FFT algorithm

Rozita Teymourzadeh
2018 Figshare  
The design has the merits of low complexity and high-speed performance. Furthermore, latency reduction is an important issue to implement the high-speed FFT on FPGA.  ...  A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented.  ...  Mohamad Amir Amini who has assisted us for completion of this dissertation.  ... 
doi:10.6084/m9.figshare.6243296 fatcat:ovrm3m52o5hljg4uk6nril7rwa

A Broadened and Deepened Anti-Jamming Technology for High-Dynamic GNSS Array Receivers

Li-wen CHEN, Jian-sheng ZHENG
2016 IEICE transactions on communications  
Also, an extensive comparison of these techniques for GNSS is established, which is evaluated from the view of convergence rate, numerical stability, computational loads, and realization complexity.  ...  The research offers a foundation of the spatial-temporal adaptive processing (STAP) practical realization and the design for new processors.  ...  ACKNOWLEDGEMENTS The author would like to thank the National Science Council of R.O.C. for their support of this work under NSC 100-2221-E-020 -027.  ... 
doi:10.1587/transcom.2015ebp3493 fatcat:z5ic3zmhbnha7bxebiqyucmnru

VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems

Mounir Arioua, Said Belkouch, Mohamed Agdad, Moha M'rabet Hassani
2011 2011 International Conference on Multimedia Computing and Systems  
An optimized implementation of the 8point FFT processor with radix-2 algorithm in R2MDC architecture is presented in this paper.  ...  The butterfly-Processing Element (PE) used in the 8-FFT processor reduces the multiplicative complexity by using a real constant multiplication in one method and eliminates the multiplicative complexity  ...  The implemented algorithm of complex multiplication used in this work uses three multiplications, one addition and two subtractions as shown in Fig. 3 .  ... 
doi:10.1109/icmcs.2011.5945661 fatcat:x6gbud3ljjeltooinc7uod6kka

Bidimensional median filter for parallel computing architectures

Ricardo M. Sanchez, Paul A. Rodriguez
2012 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
We have implemented our proposed algorithm in two parallel architectures: SIMD Intel and CUDA, which have a throughput of 12.8 and 35 ∼ 57 megapixels per second respectively.  ...  Those algorithms were formulated for scalar single processor computers, with few of them successfully adapted and implemented for computer with a parallel architecture.  ...  For the Intel implementations we can confirm the expected computational complexity: O(n) for MatLab (for k ≥ 7) and O(1) for the CTMF and PCMF algorithms.  ... 
doi:10.1109/icassp.2012.6288187 dblp:conf/icassp/SanchezR12 fatcat:mm34bx3x6fhlpafvy3pvm2seze
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