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Completely Verifying Memory Consistency of Test Program Executions

C. Manovit, S. Hangal
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.  
For popular memory models like SC and TSO, the problem of verifying correctness of an execution is known to be NP-complete.  ...  However, when intentional data races are placed in a test program, there may be many correct results according to the memory consistency model supported by the system.  ...  Related work The problem of verifying whether a multiprocessor test program execution complies with a memory consistency model was first studied by Gibbons and Korach for the SC memory model [6] .  ... 
doi:10.1109/hpca.2006.1598123 dblp:conf/hpca/ManovitH06 fatcat:meir54aldngdxcpqtmtyzxt33q

Formal Reasoning about Hardware and Software Memory Models [chapter]

Abhik Roychoudhury
2002 Lecture Notes in Computer Science  
These executable specifications can be used for exhaustive search i.e. computing all allowed behaviors of test programs under the JMM and the hardware memory models.  ...  The allowed behaviors of any multithreaded Java program on any implementation platform (multi-or uni-processor), are described in terms of a memory consistency model called the Java Memory Model (JMM).  ...  Once the JMM revision is finalized, we plan to perform a full-fledged comparison of the revised JMM with various existing multiprocessor memory models (SPARC TSO, SPARC PSO, DEC Alpha, IBM 370 etc) using  ... 
doi:10.1007/3-540-36103-0_44 fatcat:vk6jcwiq4rhypawfwagfxnoqa4

Fast complete memory consistency verification

Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
The verification of an execution against memory consistency is known to be NP-hard.  ...  LCHECK has been integrated into both pre and post silicon verification platforms of the Godson-3 microprocessor, and many bugs of memory consistency and cache coherence were found with the help of LCHECK  ...  We also thank Timothy Pinkston for his help in improving the readability of the paper.  ... 
doi:10.1109/hpca.2009.4798276 dblp:conf/hpca/ChenLHCSWP09 fatcat:uqt534rbajh6rmnkvpqvj5rf7e

A Memory Model Sensitive Checker for C# [chapter]

Thuan Quang Huynh, Abhik Roychoudhury
2006 Lecture Notes in Computer Science  
Such a memory model is typically weaker than Sequential Consistency and allows reordering of operations within a program thread.  ...  Therefore, programs verified correct by assuming Sequential Consistency (that is, each thread proceeds in program order) may not behave correctly on certain platforms!  ...  The execution model allows a program thread to either execute its next bytecode or complete one of the incomplete bytecodes.  ... 
doi:10.1007/11813040_32 fatcat:j3hj6jqtcngvtonfyf6rerhmvy

The complexity of verifying memory coherence and consistency

J.F. Cantin, M.H. Lipasti, J.E. Smith
2005 IEEE Transactions on Parallel and Distributed Systems  
The problem of testing shared memories for memory coherence and consistency is studied.  ...  The complexity of verifying consistency models is not a mere consequence of coherence, and verifying sequential consistency remains NP-Complete even after coherence has been verified.  ...  They are also grateful for the comments and suggestions of Deborah Joseph, Eric Bach, Paramjit Oberoi, Shiliang Hu, Kevin Lepak, Carl Mauer, and Alan Hu.  ... 
doi:10.1109/tpds.2005.86 fatcat:abkz5xkkbrf2phtzpasdjcusai

PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models

Daniel Lustig, Michael Pellauer, Margaret Martonosi
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
Architectural specifications such as "preserved program order" are then treated as propositions to be verified, rather than simply as assumptions.  ...  We present PipeCheck, a methodology and automated tool for verifying that a particular microarchitecture correctly implements the consistency model required by its architectural specification.  ...  This work was supported in 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014 part by C-FAR, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by  ... 
doi:10.1109/micro.2014.38 dblp:conf/micro/LustigPM14 fatcat:a5gu36zgsfhipimbsommyuwbn4

Memory model sensitive bytecode verification

Thuan Quang Huynh, Abhik Roychoudhury
2007 Formal methods in system design  
The processors allow out-of-order execution (as long as data dependencies are not violated).  ...  A = 1; flag = 1; while (flag == 0) {}; print A; || Expected value = 1 Possible printed values {0, 1} The two threads are executed on different processors.  ...  Sequential Consistency Programmer expects statements within a thread to complete in program order: Sequential Consistency 1. Each thread proceeds in program order 2.  ... 
doi:10.1007/s10703-007-0041-6 fatcat:lqk6p2cw4fd2rm7xnwdith2ezy

A Hybrid Formal Verification System in Coq for Ensuring the Reliability and Security of Ethereum-based Service Smart Contracts [article]

Zheng Yang, Hang Lei, Weizhong Qian
2020 arXiv   pre-print
The four primary components of FSPVM-E include a general, extensible, and reusable formal memory framework, an extensible and universal formal intermediate programming language denoted as Lolisa, which  ...  is a large subset of the Solidity programming language using generalized algebraic datatypes, the corresponding formally verified interpreter of Lolisa, denoted as FEther, and assistant tools and libraries  ...  Acknowledgment The authors wish to thank Marisa and Zisheng Wang for their kind assistance and LetPub (www.letpub.com) for its linguistic assistance during the preparation of this manuscript.  ... 
arXiv:1902.08726v3 fatcat:3ataiuex5jdaxpzz5uv4w6eqru

Proving Memory Safety of the ANI Windows Image Parser Using Compositional Exhaustive Testing [chapter]

Maria Christakis, Patrice Godefroid
2015 Lecture Notes in Computer Science  
We report in this paper how we proved memory safety of a complex Windows image parser written in low-level C in only three months of work and using only three core techniques, namely (1) symbolic execution  ...  at the x86 binary level, (2) exhaustive program path enumeration and testing, and (3) user-guided program decomposition and summarization.  ...  Introduction Systematic dynamic test generation [18, 9] consists of repeatedly running a program both concretely and symbolically.  ... 
doi:10.1007/978-3-662-46081-8_21 fatcat:cywxxv5moret5ncmpriu37e3ry

Efficient algorithms for verifying memory consistency

Chaiyasit Manovit, Sudheendra Hangal
2005 Proceedings of the 17th annual ACM symposium on Parallelism in algorithms and architectures - SPAA'05  
One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement.  ...  It has been shown in prior work, however, that accurately verifying such compliance even of a single execution result is an NP-complete problem, for an unlimited number of processors.  ...  Durgam Vahia, Aleksandr Gert, Rohit Kumar and Gopal Reddy have contributed substantially to the current implementation of TSOtool.  ... 
doi:10.1145/1073970.1074011 dblp:conf/spaa/ManovitH05 fatcat:7ks4xzcrwvalfo3scljn57yblq

Implementing and Evaluating a Model Checker for Transactional Memory Systems

Woongki Baek, Nathan Bronson, Christos Kozyrakis, Kunle Olukotun
2010 2010 15th IEEE International Conference on Engineering of Complex Computer Systems  
Transactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming.  ...  We also verify the serializability of TL2 and SigTM and strong isolation guarantees of SigTM.  ...  Test Program Generator To verify the serializability of TM systems, the test program generator of ChkTM uses the skeleton code shown in Figure 8 .  ... 
doi:10.1109/iceccs.2010.30 dblp:conf/iceccs/BaekBKO10 fatcat:nwyfgq6g4bc5djywxqztptyxiy

The 'test model-checking' approach to the verification of formal memory models of multiprocessors [chapter]

Ratan Nalumasu, Rajnish Ghughal, Abdel Mokkedem, Ganesh Gopalakrishnan
1998 Lecture Notes in Computer Science  
We offer a solution to the problem of verifying formal memory models of processors by combining the strengths of model-checking and a formal testing procedure for parallel machines.  ...  We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated.  ...  A1 davis and his Avalanche team for offering us the unique opportinuty to work on state-of-art processors and busses.  ... 
doi:10.1007/bfb0028767 fatcat:oj2aimybqfc43ad4lnohzfphie

Dynamic partial order reduction for relaxed memory models

Naling Zhang, Markus Kusano, Chao Wang
2015 Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI 2015  
behavior, tools which automatically explore the relaxed-memory behavior of a program can help a designer to write • As such, we require intelligent pruning methods to identify redundancies across executions  ...  a relaxed memory model is difficult. • As a result, it would be nice if we had automated testing and verification tools for multithreaded programs written under relaxed memory models • However, the observed  ...  tool • The increase in allowable behavior in the program means the verifier needs to explore a much larger state space • In esscense, the verifier needs to not only test all the sequentially consistent  ... 
doi:10.1145/2737924.2737956 dblp:conf/pldi/ZhangKW15 fatcat:cphaloq73nbpffleiwyafislom

Dynamic partial order reduction for relaxed memory models

Naling Zhang, Markus Kusano, Chao Wang
2015 SIGPLAN notices  
behavior, tools which automatically explore the relaxed-memory behavior of a program can help a designer to write • As such, we require intelligent pruning methods to identify redundancies across executions  ...  a relaxed memory model is difficult. • As a result, it would be nice if we had automated testing and verification tools for multithreaded programs written under relaxed memory models • However, the observed  ...  tool • The increase in allowable behavior in the program means the verifier needs to explore a much larger state space • In esscense, the verifier needs to not only test all the sequentially consistent  ... 
doi:10.1145/2813885.2737956 fatcat:qez33fnhjjemdos7fs675tu7k4

Efficiently and Completely Verifying Synchronized Consistency Models [chapter]

Yi Lv, Luming Sun, Xiaochun Ye, Dongrui Fan, Peng Wu
2014 Lecture Notes in Computer Science  
The physical time order information can help verifying the memory model of a multiprocessor system rather efficiently.  ...  We implement our approach in a Memory Order Dynamic Verifier (MODV). A case study with an industrial Godson-T many-core processor demonstrates the effectiveness and efficiency of our approach.  ...  A common way to verify the memory model of a multiprocessor system is by running concurrent test programs on the system and then checking whether their executions comply with the memory model under concern  ... 
doi:10.1007/978-3-319-11936-6_20 fatcat:v2rrvcpf6zbptk6ca4y42hilzu
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