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Online placement for dynamically reconfigurable devices

Ali Ahmadinia, Christophe Bobda, Jurgen Teich
2005 International Journal of Embedded Systems  
Online placement is one of these management issues that is investigated in this paper. Here we present a new approach for online placement of modules on reconfigurable devices.  ...  Reconfigurable hardware components such as FPGAs are used more and more in embedded systems, since such components offer a sufficient capacity for a complete SoC(System on a Chip) or even NoC(Network on  ...  H is the height, W the width of the reconfigurable device and n is the number of running tasks on the hardware.  ... 
doi:10.1504/ijes.2005.009947 fatcat:rlpkoo3jqbh4lafzgjmevhat3m

Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks

C. Steiger, H. Walder, M. Platzner
2004 IEEE transactions on computers  
Today's reconfigurable hardware devices have huge densities and are partially reconfigurable, allowing for the configuration and execution of hardware tasks in a true multitasking manner.  ...  In this paper, we first discuss design issues for reconfigurable hardware operating systems. Then, we focus on a runtime system for guaranteebased scheduling of hard real-time tasks.  ...  The authors discuss trade offs between reconfiguration time and circuit quality depending on the reconfiguration method used and information about the configuration sequence that is available at compile  ... 
doi:10.1109/tc.2004.99 fatcat:2gfvvj75n5ehfebym5hhtbn7ia

Design Methods and Tools for Improved Partial Dynamic Reconfiguration [chapter]

Markus Rullmann, Renate Merker
2010 Dynamically Reconfigurable Systems  
We also provide an overview about design entry, hardware task scheduling, and hardware task placement.  ...  Here we focus on the execution of the hardware tasks on the reconfigurable fabric. A hardware task is first loaded onto the reconfigurable fabric in step (c) and then the task is executed (e).  ...  It is shown how the model can be incorporated into all stages of the design optimization for reconfigurable hardware.  ... 
doi:10.1007/978-90-481-3485-4_8 fatcat:fby3cnqgybhf3eql2452why7m4

Optimizing the FPGA Implementation of HRT Systems

Marco Di Natale, Enrico Bini
2007 Real Time and Embedded Technology and Applications Symposium (RTAS), IEEE  
When implementing functions on such devices, designers can choose between hardware and software.  ...  The availability of programmable hardware devices with high density of logic elements and the possibility of implementing CPUs (called softcores) using a fraction of the FPGA area offers additional flexibility  ...  The cost of the simplistic one-dimensional model is often too high for off-line design synthesis, which is the goal of our research.  ... 
doi:10.1109/rtas.2007.25 dblp:conf/rtas/NataleB07 fatcat:7cv7wjbo4fapbnmz7y6hhauh3e

A survey on reducing reconfiguration cost: reconfigurable PID control as a special case

Rikus R. le Roux, George van Schoor, Pieter A. van Vuuren
2014 IFAC Proceedings Volumes  
Even though various survey papers exist on the topic of reconfiguration, none really focus on methods to reduce the cost of reconfiguration.  ...  Despite the numerous advantages of reconfiguration, it is only suitable for quasi-static applications with slowly changing reconfiguration criteria.  ...  Bitstream generation The bitstream contains the configuration data of the FPGA and can be generated on-line and off-line (Bruneel and Stroobandt (2008b) ).  ... 
doi:10.3182/20140824-6-za-1003.01544 fatcat:ul7mng6otre6xmi7b6b4umomwu

Mapping Recursive Functions to Reconfigurable Hardware

George Ferizis, Hossam Gindy
2006 2006 International Conference on Field Programmable Logic and Applications  
In certain instances due to constraints on hardware availability, such as a lack of hardware that properly supports runtime reconfiguration, and hardware with a low number of logic gates, results were  ...  Current Field Programmable Gate Array (FPGA) systems, in particular, allow for the rapid and cost effective implementation of hardware devices when compared to standard ASIC design, and for the increase  ...  Introduction Reconfigurable computing is a method of computing where general purpose hardware is configured for a specific task, but may be reconfigured for a different task at a later date.  ... 
doi:10.1109/fpl.2006.311226 dblp:conf/fpl/FerizisE06 fatcat:xwvkiwrcwbegjmfrat6wb7ewnm

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

Adewale Adetomi, Godwin Enemali, Xabier Iturbe, Tughrul Arslan, Didier Keymeulen
2018 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
This thesis presents novel techniques for the management of hardware task placement on COTS reconfigurable devices for high performance and reliability.  ...  For many reconfigurable hardware such as COTS FPGAs, this mean that it is often infeasible to change the physical layout of the hardware task in runtime as Unlike task placement on homogeneous FPGAs where  ... 
doi:10.1109/ahs.2018.8541369 dblp:conf/ahs/AdetomiEIAK18 fatcat:kr7xdsvbaveqxplr6iwpdpx4me

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. Böhm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu (+9 others)
2015 Microprocessors and microsystems  
FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose  ...  The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems.  ...  Acknowledgement This work was supported by the European Commission -Belgium in the context of FP7 FASTER project (#287804).  ... 
doi:10.1016/j.micpro.2014.09.006 fatcat:35jcur7nljhw7hqletmdrqjhum

Dynamic Hardware Development

Stephen Craven, Peter Athanas
2008 International Journal of Reconfigurable Computing  
While the trend in digital design is towards higher levels of design abstractions, forgoing hardware description languages in some cases for high-level languages, the development of a reconfigurable design  ...  of dynamically reconfigurable hardware solely from a specification written in C.  ...  Higher ideal aspect ratios are used for the Virtex-II families to minimize reconfiguration overhead. waste is a measure of extra resources within the placement that will not be utilized on the device.  ... 
doi:10.1155/2008/901328 fatcat:3itrrcxyhjaijh2fjkhtsap2jy

Context-Aware Speculative Prefetch for Soft Real-Time Applications

Adrian Lifa, Petru Eles, Zebo Peng
2012 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications  
One method to overcome this problem is configuration prefetching, which tries to reduce the reconfiguration penalty by preloading modules on the FPGA before they are needed, and overlapping the reconfiguration  ...  Dynamically reconfigurable computing devices have the ability to adapt their hardware to application demands, providing the performance of hardware acceleration, as well as high flexibility, at competitive  ...  PREVIOUS WORK One line of previous work related to ours was done in the area of partitioning and statically scheduling task graphs for FPGA-based architectures.  ... 
doi:10.1109/rtcsa.2012.24 dblp:conf/rtcsa/LifaEP12 fatcat:yzshfi62pjcznhkhysxqjiysiu

Subframe multiplexing for FPGA manufacturing test configuration

Erik Chmelar
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
One of the FPGA co-simulations is over 3 times faster running over a TCP/IP network distance off approximately 600 kilometres, than running a normal Simulink simulation on the host PC.  ...  The DWT is performed using the hardware-efficient Lifting Scheme method versus the traditional convolution-based methods minimizing memory requirements, eliminating the need for expensive floating-point  ...  Therefore, on-line scheduling of tasks in the spatial and temporal domains becomes possible, enabling the implementation of virtual hardware concept.  ... 
doi:10.1145/968280.968315 dblp:conf/fpga/Chmelar04 fatcat:bkkwooxvszbvlfrg4b7h5svtvi

Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration

Shannon Koh, Oliver Diessel
2010 ACM Transactions on Reconfigurable Technology and Systems  
A complete bitstream for a device is comprised of the bitstream for the static region plus an initial bitstream for each of the PRRs.  ...  However, the algorithm proposed for graph merging in [Koh and Diessel 2007] was based on a greedy method and is not optimal. In addition, a more thorough assessment of graph merging was desired.  ...  We have therefore sought faster approximate methods that provide reasonable feedback on the potential to successfully map a merged subsequence to the target device.  ... 
doi:10.1145/1661438.1661442 fatcat:2vlbsih3vfapzgfh7qfgnkq3sy

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems [article]

Daniel Ziener
2018 arXiv   pre-print
In this treatise, my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined.  ...  The efficiency of reconfigurable systems can be improved by loading optimized data paths on-the-fly on an FPGA fabric.  ...  The research has been carried out in collaboration with several doctoral researchers, master and bachelor students from my research group Reconfigurable Computing. In  ... 
arXiv:1809.11156v1 fatcat:6ttulp2tancyvds7fk2coxoptq

Server-based execution of periodic tasks on dynamically reconfigurable hardware

K. Danne, R. Mühlenbernd, M. Platzner
2007 IET Computers & Digital Techniques  
A prototype system that executes a set of periodic real-time tasks utilising dynamic hardware reconfiguration is presented.  ...  The proposed scheduling technique, merge server distribute load (MSDL), is not only able to give an offline guarantee for the feasibility of the task set, but also minimises the number of device configurations  ...  Techniques for off-line placement and scheduling are described in [7] . The goal is to minimise the total execution time of a given task graph on an FPGA.  ... 
doi:10.1049/iet-cdt:20060186 fatcat:idodhasnhzdydomnlfmtxceive

Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

Jose Luis Nunez-Yanez, Mohammad Hosseinabady, Arash Beldachi
2016 IEEE transactions on computers  
The nominal power line is based on a fixed nominal voltage of 1.0 V.  ...  The timing overhead required to turn off and turn on the FPGA has been measured to around to 3 msec. The PL must be fully reconfigured after turning on before it can be used again in the application.  ...  with higher accuracy the thresholds in which the different techniques are more effective and validating the work with other acceleration cores that can be configured with different levels of complexity  ... 
doi:10.1109/tc.2015.2435771 fatcat:ydgsir3i3bbvtibbbiamdrica4
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