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Compiling for the Impulse memory controller

Xianglong Huang, Zhenlin Wang, K.S. McKinley
Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques  
The Impulse memory controller provides an interface for remapping irregular or sparse memory accesses into dense accesses in the cache memory.  ...  We implement the cost models and generate the appropriate Impulse system calls in the Scale compiler framework.  ...  Introduction In this paper, we develop, implement, and evaluate compiler cost models to drive compiler optimizations for the Impulse memory controller [2, 3, 15] .  ... 
doi:10.1109/pact.2001.953295 dblp:conf/IEEEpact/HuangWM01 fatcat:ljoi3goco5f3lo364efhbaubfu

Memory System Support for Irregular Applications [chapter]

John Carter, Wilson Hsieh, Mark Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael Parker, Lambert Schaelicke, Leigh Stoller, Terry Tateyama
1998 Lecture Notes in Computer Science  
In this paper we describe the optimizations that the Impulse controller supports for sparse matrix-vector product, an important computational kernel, and outline the transformations that the compiler and  ...  The Impulse con gurable memory controller will enable signi cant performance improvements for irregular applications, because it can be congured to optimize memory accesses on an application-by-application  ...  Figures 3 and 4illustrate the code generated for the inner loop of conjugate gradient b y a compiler designed to exploit the Impulse memory controller.  ... 
doi:10.1007/3-540-49530-4_2 fatcat:gmlkfqnwwvbqpnimhn56ysryu4

Trident: From High-Level Language to Hardware Circuitry

Justin L. Tripp, Maya B. Gokhale, Kristopher D. Peterson
2007 Computer  
At the root of this technology are the Impulse C compiler and related tools and the Impulse application programmer interface (API).  ...  Impulse C also includes platform support packages that simplify C-to-hardware compilation for specific FPGA-based platforms.  ...  Tripp is a technical staff member on the Application-Specific Architectures Team in the Advanced  ... 
doi:10.1109/mc.2007.107 fatcat:yamhfranjrfurfci54l2mnaafe

The Impulse memory controller

Lixin Zhang, Zhen Fang, M. Parker, B.K. Mathew, L. Schaelicke, J.B. Carter, W.C. Hsieh, S.A. McKee
2001 IEEE transactions on computers  
The Impulse design does not require any modification to processor, cache, or bus designs since all the functionality resides at the memory controller.  ...  Alternatively, Impulse can be used by the OS for dynamic superpage creation; the best policy for creating superpages using Impulse outperforms previously known superpage creation policies.  ...  The Impulse memory controller maintains its own page tables for shadow memory mappings.  ... 
doi:10.1109/12.966490 fatcat:aorvqc2pm5erbotcexbgbpks4i

Impulse: building a smarter memory controller

J. Carter, W. Hsieh, L. Stoller, M. Swanson, Lixin Zhang, E. Brunvand, A. Davis, Chen-Chi Kuo, R. Kuramkote, M. Parker, L. Schaelicke, T. Tateyama
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses.  ...  Impulse is a new memory system architecture that adds two important features to a traditional memory controller.  ...  Acknowledgments We thank Sally McKee, Massimiliano Poletto, and Llewellyn Reese for comments on drafts of this paper, and Chris Johnson for his assistance in providing us information on conjugate gradient  ... 
doi:10.1109/hpca.1999.744334 dblp:conf/hpca/CarterHSSZBDKKPST99 fatcat:qvr2a6fb6neuziaubqvuxgetni

Impulse: Memory System Support for Scientific Applications

John B. Carter, Wilson C. Hsieh, Leigh B. Stoller, Mark Swanson, Lixin Zhang, Sally A. McKee
1999 Scientific Programming  
Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses.  ...  For instance, Impulse decreases the running time of the NAS conjugate gradient benchmark by 67%.  ...  Acknowledgments We thank Erik Brunvand, Al Davis, Chris Johnson, Chen-Chi Kuo, Ravindra Kuramkote, Mike Parker, Lambert Schaelicke, Terry Tateyama, Massimiliano Poletto, and Llewellyn Reese for their assistance  ... 
doi:10.1155/1999/209416 fatcat:l34sty2eybaodltrtvl5spdp7i

Advanced accelerator control and instrumentation modules based on FPGA

P. Messmer, V. Ranjbar, D. Wade-Stein, P. Schoessow, J. G. Power
2007 2007 IEEE Particle Accelerator Conference (PAC)  
To facilitate the use of FPGAs in control systems we are developing a library of software tools based on ImpulseC, a high level subset of the C language specifically designed for FPGA programming.  ...  Here we present initial results of algorithms of relevance to controls applications implemented in Impulse C.  ...  The Impulse C compiler translates the software processes into native code for the host CPU, while the hardware processes are compiled to produce FPGA-ready hardware definitions.  ... 
doi:10.1109/pac.2007.4440260 fatcat:rhnkv2e46vhivii56wrbglgw7a

Design of Piezoelectric Energy Harvester and Power Conditioning

D. Meena, P. Jegan, R. Puviyarasan, R. Sathish
2020 International Journal of Scientific Research in Science Engineering and Technology  
The output of the Ultralow Power Converter is given to the Relay for the switching unit to store energy in a DC Power Bank and the stored energy is inverted to AC voltage  ...  The outputs of transducers are also given to micro controller. The obtained energy is boosted up using Booster Ultra Low Power Converter.  ...  For example: • Direct Cx51 to generate a listing file • Control the information included in the object file • Specify code optimization and memory models Running Cx51 from the Command Prompt  ... 
doi:10.32628/ijsrset2072102 fatcat:pgc2tto3ivfrphqw66a2tpihtq

High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations

Diego Sanchez-Roman, Gustavo Sutter, Sergio Lopez-Buedo, Ivan Gonzalez, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios
2011 IEEE Design & Test of Computers  
Unfortunately, the huge computational costs of CFD prevent it from being a valid tool for the entire design process.  ...  Fortunately, this drawback is being reduced, thanks to the advent of hardware compilers from high-level languages (HLLs), typically C or C dialects. 7,8 Although HLLs reduce development time, manual optimizations  ...  Acknowledgments This work was supported by the Dovres (Design Optimization by Virtual Reality Simulation) project under the Airbus FuSim-E (Future Simulation Concept) Programme initiative.  ... 
doi:10.1109/mdt.2011.88 fatcat:fsclf5r4lveq5cn7scecwiirxe

The Design of a Portable ECG Measurement Instrument Based on a GBA Embedded System

Jia-Ren Chang Chien, Cheng-Chi Tai
2006 2006 IEEE International Conference on Industrial Technology  
: This feature is used to perform 'boot loader' functions for devices without this feature  ALTERA EPM3060ATC100 CPLD used  Function: Compiled code from computer would be put in GBA memory via  ...  Right & Left Atria stimulated (depolarized) & contract for some time pumping blood into ventricles ( P Wave)  Impulse travels from SA to AV node thru Conduction pathways  Impulse slow down briefly,  ... 
doi:10.1109/icit.2006.372490 fatcat:2eyume7lmzeujg3obyrvxjavuu

H.265 Inverse Transform FPGA implementation in Impulse C

Sławomir Cichoń, Marek Gorgoń
2017 Proceedings of the 2017 Federated Conference on Computer Science and Information Systems  
It is one of main research topics for FPGA engineers working on image compression algorithms.  ...  This paper presents FPGA implementation of HEVC 2D Inverse DCT transform implemented on Xilinx Virtex-6 using Impulse C high level language.  ...  ACKNOWLEDGMENT Authors would like to thank Impulse Accelerated Technologies (http://www.impulseaccelerated.com) for providing software license for the CoDeveloper Integrated Development Environment.  ... 
doi:10.15439/2017f185 dblp:conf/fedcsis/CichonG17 fatcat:wvkqthmnhnahfhw66ygrqxgwra

Dynamic access ordering for streamed computations

D.A.B. Weikle, S.I. Hong, M.H. Salinas, R.H. Klenke, J.H. Aylor, W.A. Wulf, S.A. McKee
2000 IEEE transactions on computers  
We describe a Stream Memory Controller (SMC) system that combines compile-time detection of streams with execution-time selection of the access order and issue.  ...  The SMC is practical to implement, using existing compiler technology and requiring only a modest amount of specialpurpose hardware.  ...  Intel also contributed the i860 processor and board. The Oregon Graduate Institute of Science and Technology provided resources and partial support for Sally McKee during part of this research.  ... 
doi:10.1109/12.895941 fatcat:gj5dhemidrgv3ewc5nwlht2vzy

The Promise of High-Performance Reconfigurable Computing

T. El-Ghazawi, E. El-Araby, Miaoqing Huang, K. Gaj, V. Kindratenko, D. Buell
2008 Computer  
The implementation is quite modular and capitalizes on the use of source-tosource UPC compilers.  ...  Based on the parallel characteristics exhibited at the UPC program, code sections that are amenable to hardware implementation are extracted and diverted to a C-tohardware compiler.  ...  The language also offers a rich range of synchronization and memory consistency control constructs. Proposed Solutions The productivity problem of HPRCs can be stated as follows.  ... 
doi:10.1109/mc.2008.65 fatcat:6mwj5aeb6zczdd5it5rwngfwpu

Proposal of Automatic FPGA Offloading for Applications Loop Statements [article]

Yoji Yamato
2020 arXiv   pre-print
Partly of the offloading to the GPU was automated previously.  ...  I evaluate the effectiveness of the proposed method using existing applications.  ...  impulse response filter. 16 for MRI-Q.  ... 
arXiv:2004.08548v1 fatcat:yuywyjk2irhkjpoiii4lp4xini

Improving the Performance of Shared Memory Communication in Impulse C

Xi Jin, Nan Guan, Mingsong Lv, Qingxu Deng
2010 IEEE Embedded Systems Letters  
But the communication mechanisms of Impulse C are mainly designed for versatility, and the resources within the FPGA chip is not fully utilized.  ...  In this article, we present a improved implementation of the shared memory communication in Impulse C by utilizing both ports of the dual-port BRAM.  ...  In the original Impulse C implementation, processes can only access the shared memory via OPB (On-chip Peripheral Bus) and the OPB memory interface controller.  ... 
doi:10.1109/les.2010.2048010 fatcat:r6appsyhlvbwdm3tks5brrahye
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