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A New Multi-Target Compiler Architecture for Edge-Devices and Cloud Management

Erhan GÖKÇAY
2021 GAZI UNIVERSITY JOURNAL OF SCIENCE  
This paper introduces a new compiler architecture to control and program edge-devices from a single source code.  ...  The source code can be distributed to multiple edge-devices using simple compiler directives, and the transfer and communication of the source code with multiple devices are handled transparently.  ...  Individual compilation for different architectures poses no problem since there are compilers for any typical architecture and processor/controller.  ... 
doi:10.35378/gujs.803726 fatcat:ipfkppgzcjgmrellpx6y4ya72e

Edge-centric modulo scheduling for coarse-grained reconfigurable architectures

Hyunchul Park, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-seok Kim
2008 Proceedings of the 17th international conference on Parallel architectures and compilation techniques - PACT '08  
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing the potential for high computation throughput, scalability, low cost, and energy efficiency.  ...  With edge-centric modulo scheduling (EMS), placement is a by-product of the routing process, and the schedule is developed by routing each edge in the dataflow graph.  ...  For the mesh-plus architecture, EMS achieves an average ILP of 9.6 across all the loops. The final measurement performed is compilation time.  ... 
doi:10.1145/1454115.1454140 dblp:conf/IEEEpact/ParkFMOKK08 fatcat:uvwjgh3rkzgifeh64jgalnexkq

Compiling for EDGE Architectures

A. Smith, J. Gibson, B. Maher, N. Nethercote, B. Yoder, D. Burger, K.S. McKinle, J. Burrill
International Symposium on Code Generation and Optimization (CGO'06)  
In EDGE architectures, the compiler breaks a program into a sequence of structured blocks that the hardware executes atomically.  ...  Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction -level parallelism with energy efficiency.  ...  An EDGE architecture has two distinct features that require new compiler support.  ... 
doi:10.1109/cgo.2006.10 dblp:conf/cgo/SmithGMNYBMB06 fatcat:bpuacj2spvhndbtd36pqfzyzm4

Efficient edge profiling for ILP-processors

A.E. Eichenberger, S.M. Lobo
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)  
Compilers for VLIW and superscalar machines increasingly use dynamic application behavior or profiling information in optimizations such as instruction scheduling, speculative code motion, and code layout  ...  For an 8-wide issue machine, measurements for the SPECint95 benchmarks indicate a 10-fold reduction in overhead (from 32.8% to 3.3%), when compared with previous techniques.  ...  Acknowledgements We would like to acknowledge the help of Chao-Ying Fu, for his implementation of the traditional edge profiling technique used in this paper, as well as an initial version of the Probe  ... 
doi:10.1109/pact.1998.727264 dblp:conf/IEEEpact/EichenbergerL98 fatcat:r46exycylnbvpgjnk5y5qnnwkq

Static placement, dynamic issue (SPDI) scheduling for EDGE architectures

R. Nagarajan, S.K. Kushwaha, D. Burger, K.S. McKinley, C. Lin, S.W. Keckler
Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.  
We evaluate a range of SPDI scheduling algorithms executing on an Explicit Data Graph Execution (EDGE) architecture.  ...  Technology trends present new challenges for processor architectures and their instruction schedulers.  ...  architectures that use other execution models are certainly possible; for example, WaveScalar [32] can be characterized as a DPDI EDGE architecture.  ... 
doi:10.1109/pact.2004.1342543 fatcat:eq7nnk26pjfb3lfahgmmhjnxte

Scaling to the end of silicon with EDGE architectures

D. Burger, S.W. Keckler, K.S. McKinley, M. Dahlin, L.K. John, C. Lin, C.R. Moore, J. Burrill, R.G. McDonald, W. Yoder
2004 Computer  
The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next  ...  To demonstrate the tractability of the compiler analyses needed for EDGE architectures, we retargeted the Scale research compiler 3 to generate optimized TRIPS code.  ...  For current and future technologies, EDGE architectures and their ISAs provide a proper division between the compiler and architecture, matching their responsibilities to their intrinsic capabilities,  ... 
doi:10.1109/mc.2004.65 fatcat:kvdia4bm2velfnlle57bt6qcpy

Merging Head and Tail Duplication for Convergent Hyperblock Formation

Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley
2006 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)  
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance.  ...  Simulation results for an EDGE architecture show that convergent hyperblock formation improves code quality over discrete-phase approaches with heuristics for VLIW and EDGE.  ...  Branch predictability: Removing conditional branches is important for EDGE architectures because of their large instruction windows.  ... 
doi:10.1109/micro.2006.34 dblp:conf/micro/MaherSBM06 fatcat:sqwzvkxnf5fango7zbiotad2ra

A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template

Akira Hatanaka, Nader Bagherzadeh
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
In this paper, we present an efficient modulo scheduling algorithm for a CGRA template.  ...  Compilation onto CGRAs is still an open problem. Several groups have proposed algorithms that software pipeline loops onto CGRAs.  ...  Compilers for CGRAs Compilation onto CGRAs has been a topic of active research during the last few years.  ... 
doi:10.1109/ipdps.2007.370371 dblp:conf/ipps/HatanakaB07 fatcat:xvj545rqdfecvfyepv6tcxffxm

Domain-Specific Quantum Architecture Optimization [article]

Wan-Hsuan Lin, Bochen Tan, Murphy Yuezhen Niu, Jason Kimko, Jason Cong
2022 arXiv   pre-print
For the QCNN circuit, architecture optimization improves fidelity by 11% on the heavy-hexagon architecture and 605% on the grid architecture.  ...  It is the first work that (1) provides performance guarantees by integrating architecture optimization with an optimal compiler, (2) evaluates the impact of connectivity customization under a realistic  ...  Fig. 10 and Fig. 11 illustrate the results for QAOA compiled for the optimized grid-based architectures.  ... 
arXiv:2207.14482v1 fatcat:osxq5nbvard3pl443lgab5qpce

Placement for configurable dataflow architecture

Mongkol Ekpanyapong, Michael Healy, Sung Kyu Lim
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
In this paper, we propose a set of placement algorithms for generic dataflow architectures.  ...  As wire delay increasingly becomes a significant performance bottleneck in monolithic architectures, there is a strong motivation to move to Dataflow Architectures.  ...  We also would like to thank the MONARCH team for its continued support and ongoing contributions to this effort.  ... 
doi:10.1145/1120725.1120840 dblp:conf/aspdac/EkpanyapongHL05 fatcat:ut3yzn4ctnf7xjsttb3qrx32ji

Efficient program partitioning based on compiler controlled communication [chapter]

Ram Subramanian, Santosh Pande
1999 Lecture Notes in Computer Science  
We propose a compiler driven approach that con gures underlying architecture to support a given communication mechanism.  ...  We i n troduce the concept of behavioral edges between edges and nodes in the task graph for capturing the interactions between computation and communication through parametric functions.  ...  However, the use of compilation techniques for estimation was a complex problem due to the complex run time behaviors of the architectures.  ... 
doi:10.1007/bfb0097884 fatcat:owyojrhpinh4lcxgjud7npenl4

The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors

Bertrand A. Maher, Katherine E. Coons, Kathryn S. McKinley, Doug Burger
2011 2011 15th Workshop on Interaction between Compilers and Computer Architectures  
This paper studies the balance of complexity and capability between EDGE architectures and compilers.  ...  (3) What architecture and compiler support do these designs require?  ...  This result motivates an investigation of compiler support for such architectures.  ... 
doi:10.1109/interact.2011.17 dblp:conf/IEEEinteract/MaherCMB11 fatcat:g2xvoea435gldesvdpkhyfm6rq

Compiling parallel applications to Coarse-Grained Reconfigurable Architectures

Mohammed Ashraful Alam Tuhin, Theodore S. Norvell
2008 Canadian Conference on Electrical and Computer Engineering (CCECE)  
In this paper a novel approach for compiling parallel applications to a target Coarse-Grained Reconfigurable Architecture (CGRA) is presented.  ...  We have given a formal definition of the compilation problem for the CGRA. The application will be written in HARPO/L, a parallel object oriented language suitable for hardware.  ...  for all edges e ∈ E.  ... 
doi:10.1109/ccece.2008.4564838 fatcat:tb75l6myovhj3ipwu4nfpz474m

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

Girish Venkataramani, Walid Najjar, Fadi Kurdahi, Nader Bagherzadeh, Wim Bohm
2001 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01  
This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and map the application onto the Morphosys architecture.  ...  Morphosys is a reconfigurable computer architecture that supports a data-parallel, SIMD computational model.  ...  This paper describes a compiler framework for mapping applications written in SA-C for execution on the Morphosys architecture.  ... 
doi:10.1145/502217.502235 dblp:conf/cases/VenkataramaniNKBB01 fatcat:rgrxe4bepzdu3ppwjqirb7pspu

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

Girish Venkataramani, Walid Najjar, Fadi Kurdahi, Nader Bagherzadeh, Wim Bohm
2001 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01  
This paper describes a compiler framework to analyze SA-C programs, perform optimizations, and map the application onto the Morphosys architecture.  ...  Morphosys is a reconfigurable computer architecture that supports a data-parallel, SIMD computational model.  ...  This paper describes a compiler framework for mapping applications written in SA-C for execution on the Morphosys architecture.  ... 
doi:10.1145/502231.502235 fatcat:2wolpe2czvbftpldhbnja6ukou
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