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Compiler support for speculative multithreading architecture with probabilistic points-to analysis

Peng-Sheng Chen, Ming-Yu Hung, Yuan-Shin Hwang, Roy Dz-Ching Ju, Jenq Kuen Lee
2003 Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '03  
First probabilistic points-to analysis is performed to estimate the probabilities of points-to relationships in case there are pointer references in programs, and then the degree of dependences between  ...  Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically.  ...  Probabilistic point-to analysis will also be important for data speculations and code specializations on advanced architectures.  ... 
doi:10.1145/781498.781502 dblp:conf/ppopp/ChenHHJL03 fatcat:ekmlqqnonbe4piyuakap6xvtim

Interprocedural probabilistic pointer analysis

Peng-Sheng Chen, Yuan-Shin Hwang, R.D.-C. Ju, J.K. Lee
2004 IEEE Transactions on Parallel and Distributed Systems  
This paper addresses this issue by proposing a probabilistic points-to analysis technique to compute the probability of every points-to relationship at each program point.  ...  Consequently, it is essential for compilers to incorporate pointer analysis techniques that can estimate the possibility for every points-to relationship that it would hold during the execution.  ...  This technique has been applied to the speculative multithreading architecture to demonstrate that a compiler can achieve speedups by executing speculative threads when the possibilities are low and can  ... 
doi:10.1109/tpds.2004.56 fatcat:jvnptz7lb5bv7olpvv44g4hdli

Probabilistic Alias Analysis for Parallel Programming in SSA Forms [article]

Mohamed A. El-Zawawy, Mohammad N. Alanazi
2014 arXiv   pre-print
However most of the results of existing techniques for alias analysis are not precise enough compared to needs of modern compilers.  ...  This paper presents a new probabilistic approach for alias analysis of parallel programs.  ...  The authors acknowledge the support (grants numbers 340918 & 330911) of the deanship of scientific research of Al Imam Mohammad Ibn Saud Islamic University (IMSIU).  ... 
arXiv:1405.4401v1 fatcat:6ihi5q3yqrasjm5zvyj2gd7clu

Accurate branch prediction for short threads

Bumyong Choi, Leo Porter, Dean M. Tullsen
2008 Proceedings of the 13th international conference on Architectural support for programming languages and operating systems - ASPLOS XIII  
Using a Speculative Multithreaded (SpMT) architecture as an example of a system which generates shorter threads, this work examines techniques to improve branch prediction accuracy when a new thread begins  ...  Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose parallelism.  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful insights.  ... 
doi:10.1145/1346281.1346298 dblp:conf/asplos/ChoiPT08 fatcat:2tq33po525dd5ksn7fnaladab4

Accurate branch prediction for short threads

Bumyong Choi, Leo Porter, Dean M. Tullsen
2008 SIGARCH Computer Architecture News  
Using a Speculative Multithreaded (SpMT) architecture as an example of a system which generates shorter threads, this work examines techniques to improve branch prediction accuracy when a new thread begins  ...  Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose parallelism.  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful insights.  ... 
doi:10.1145/1353534.1346298 fatcat:lgccezyrcjagjoopui3ytuxawm

Accurate branch prediction for short threads

Bumyong Choi, Leo Porter, Dean M. Tullsen
2008 ACM SIGOPS Operating Systems Review  
Using a Speculative Multithreaded (SpMT) architecture as an example of a system which generates shorter threads, this work examines techniques to improve branch prediction accuracy when a new thread begins  ...  Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose parallelism.  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful insights.  ... 
doi:10.1145/1353535.1346298 fatcat:d6ejoxszkzdgvatavunmxekjay

Accurate branch prediction for short threads

Bumyong Choi, Leo Porter, Dean M. Tullsen
2008 SIGPLAN notices  
Using a Speculative Multithreaded (SpMT) architecture as an example of a system which generates shorter threads, this work examines techniques to improve branch prediction accuracy when a new thread begins  ...  Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose parallelism.  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful insights.  ... 
doi:10.1145/1353536.1346298 fatcat:6qp33uprcngfrihhaccddqchiy

A Survey on Thread-Level Speculation Techniques

Alvaro Estebanez, Diego R. Llanos, Arturo Gonzalez-Escribano
2016 ACM Computing Surveys  
Thread-Level Speculation (TLS) is a promising technique that allows the parallel execution of sequential code without relying on a prior, compile-time dependence analysis.  ...  COST Program Action IC1305: Network for Sustainable Ultrascale Computing (NESUS).  ...  ACKNOWLEDGMENTS This research has been partially supported by MICINN (Spain) and ERDF program of the European Union: HomProg-HetSys project (TIN2014-58876-P), CAPAP-H5 network (TIN2014-53522-REDT), and  ... 
doi:10.1145/2938369 fatcat:yqqyjoaidvci3d4dyuw2jc2p2i

A software-defined communications baseband design

J. Glossner, D. Iancu, Jin Lu, E. Hokenek, M. Moudgill
2003 IEEE Communications Magazine  
In this paper we discuss a baseband solution for an SDR system and describe a 2Mbps WCDMA design with GSM/GPRS and 802.11b capability that executes all physical layer processing completely in software.  ...  Our solution is programmed in C and executed on a multithreaded processor in real-time.  ...  On DSPs which do support 32-bit floating point, precision analysis is still required. For algorithm design, tensor algebra has been used [3] .  ... 
doi:10.1109/mcom.2003.1166669 fatcat:ulgis2pdhzd3niw2vwvc3p5spa

A compiler cost model for speculative parallelization

Jialin Dou, Marcelo Cintra
2007 ACM Transactions on Architecture and Code Optimization (TACO)  
This paper proposes a novel compiler static cost model of speculative multithreaded execution that can be used to predict the resulting performance.  ...  Conf. on Parallel Architectures and Compilation Techniques (PACT 2004).  ...  There has also been some work on compiler support for speculative multithreading based on "helper threads" [Quinones et al. 2005 ].  ... 
doi:10.1145/1250727.1250732 fatcat:miha63jvh5f25o6kzulswlfmy4

ASC

Amos Waterland, Elaine Angelino, Ryan P. Adams, Jonathan Appavoo, Margo Seltzer
2014 Proceedings of the 19th international conference on Architectural support for programming languages and operating systems - ASPLOS '14  
Each instruction execution in this model moves the system from its current point in state space to a deterministic subsequent point.  ...  We have implemented our system using a functional simulator that emulates the x86 instruction set, including a collection of state predictors and a mechanism for speculatively executing threads that explore  ...  Acknowledgments The authors would like to thank Gerald Jay Sussman  ... 
doi:10.1145/2541940.2541985 dblp:conf/asplos/WaterlandAAAS14 fatcat:hv5jp5ep25ebnmptpmcy6ltmim

The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors

Bertrand A. Maher, Katherine E. Coons, Kathryn S. McKinley, Doug Burger
2011 2011 15th Workshop on Interaction between Compilers and Computer Architectures  
(3) What architecture and compiler support do these designs require?  ...  We propose hand-crafted and learned compiler policies for block formation. We find the best policies provide significant advantages of up to a factor of 3 in some configurations.  ...  Acknowledgments This work is supported by NSF SHF-0910818, NSF CSR-0917191, NSF CCF-0811524, NSF CNS-0719966, NSF CCF-0429859, Intel, IBM, CISCO, Google, Microsoft, and a Microsoft Research fellowship.  ... 
doi:10.1109/interact.2011.17 dblp:conf/IEEEinteract/MaherCMB11 fatcat:g2xvoea435gldesvdpkhyfm6rq

HAFT

Dmitrii Kuvaiskii, Rasha Faqeh, Pramod Bhatotia, Pascal Felber, Christof Fetzer
2016 Proceedings of the Eleventh European Conference on Computer Systems - EuroSys '16  
HAFT utilizes instruction-level redundancy for fault detection and hardware transactional memory for fault recovery. We evaluated HAFT with Phoenix and PARSEC benchmarks.  ...  We present HAFT, a fault tolerance technique using hardware extensions of commodity CPUs to protect unmodified multithreaded applications against such corruptions.  ...  We thank Norman Rink for his help with the LLVM compiler backend.  ... 
doi:10.1145/2901318.2901339 dblp:conf/eurosys/KuvaiskiiFBFF16 fatcat:rvirzztinzcgpoi52iiy7dclnq

Dynamically dispatching speculative threads to improve sequential execution

Yangchun Luo, Antonia Zhai
2012 ACM Transactions on Architecture and Code Optimization (TACO)  
With the help of the runtime evaluation, where and how to create speculative threads is better determined.  ...  Existing approaches have focused on using the compilers to select sequential program regions to apply TLS.  ...  Architectural Support for Speculation Speculative threads are supported on a Chip-Multiprocessor (CMP) with the STAM-Pede extension [Steffan et al. 2000 [Steffan et al. , 2005]] .  ... 
doi:10.1145/2355585.2355586 fatcat:6wgyilas3fatlar57xffcc556i

Building timing predictable embedded systems

Philip Axer, Christine Rochange, Maurice Sebastian, Reinhard Von Hanxleden, Reinhard Wilhelm, Wang Yi, Rolf Ernst, Heiko Falk, Alain Girault, Daniel Grund, Nan Guan, Bengt Jonsson (+2 others)
2014 ACM Transactions on Embedded Computing Systems  
Perhaps paradoxically, this problem has become more difficult by the introduction of performanceenhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large  ...  Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori.  ...  Thus, it is desirable to have a WCET-aware compiler in order to support compilation for timing predictable systems.  ... 
doi:10.1145/2560033 fatcat:vyvehgnkxfdmnbs2wcwada3sxi
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